Circuit for establishing accurate sample timing

Details Circuit for establishing accurate sample timing Circuit for establishing accurate sample timing

1984-08-30

1986-03-11

LaRoche, Eugene R.

Demodulators

Amplitude modulation demodulator

Having specific distortion, noise or other interference...

329110, 329122, 329135, 375 39, 375 81, 455214, 455337, H03D 300, H03D 318

Patent

active

045756821

ABSTRACT:
In order to establish accurate sample timing in a digital demodulator which forms part of an orthogonally multiplexed parallel data transmission system, two second-order PLLs are arranged after a demodulating section of the digital demodulator so as to receive baseband signals of corresponding pilot channels. The two second-order PLLs each includes an integrator. These integrators apply the outputs thereof to a subtracter which applies the subtraction result to a voltage-controlled oscillator in order to establish the accurate sample timing.

REFERENCES:
patent: 4466109 (1984-08-01), Sari

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