Circuit for enabling a cache using a flush input to circumvent a

Details Circuit for enabling a cache using a flush input to circumvent a Circuit for enabling a cache using a flush input to circumvent a

1989-06-20

1992-03-17

Lee, Thomas C.

Boots, shoes, and leggings

36424341, 3642663, 364270, 3642714, 3649642, 3649571, 3642542, 3642543, 3649575, 3649602, 3642511, 3642513, 3649606, 364DIG1, G06F 1206, G06F 9312, G06F 112

Patent

active

050975323

ABSTRACT:
A circuit for generating a synchronized flush signal for use with a cache controller which samples the noncachable address input too late for that input to be used to disable the cache controller is described. The circuit synchronizes a memory-mapped register bit with the internal clock signal in the cache controller to insure setup and hold times and proper phasing. The use of the synchronized flush signal overcomes coherency problems with the noncachable input.

REFERENCES:
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patent: 4622631 (1986-11-01), Frank et al.
patent: 4713755 (1987-12-01), Worley, Jr. et al.
patent: 4755930 (1988-07-01), Wilson, Jr. et al.
patent: 4775955 (1988-10-01), Liu
patent: 4802120 (1989-01-01), McCoy
patent: 4827401 (1989-05-01), Hrustich et al.
patent: 4833601 (1989-05-01), Barlow et al.
Intel Corporation, Intel 1990 Microprocessor and Peripheral Handbook, pp. 4-343-4-409: 1990.

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