Circuit for eliminating off-chip to on-chip clock skew

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

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327292, 327237, H03K 513, H03K 514

Patent

active

053940245

ABSTRACT:
A circuit eliminates clock skew between an off-chip clock signal originating off an integrated circuit and an on-chip clock signal produced on the integrated circuit. The on-chip clock signal is produced by phase delaying the off-chip clock signal. A first delay path and a second delay path each phase delay the off-chip clock signal an identical amount. A multiplexor selects one of the delay paths to produce the on-chip clock signal. When phase delay through the first delay path is adjusted, the multiplexor selects the second delay path. When phase delay through the second delay path is adjusted, the selection means selects the first delay path. A phase detector and filter circuit generates control signals which indicate, based on phase difference between the off-chip clock signal and the on-chip clock signal, when to increase and when to decrease the phase delay through the delay paths.

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patent: 5192886 (1993-03-01), Wetlanfer
patent: 5223755 (1993-06-01), Richley
patent: 5237224 (1993-08-01), DeLisle et al.
M. Johnson, et al., A Variable Delay Line PLL for CPU-Coprocessor Synchronization, IEEE Journal of Solid State Circuits, vol. 23, No. 5, Oct. 1988, p. 1218.
D. Jeong et al., Design of PLL-Based Clock Generation circuits, IEEE Journal of Solid State Circuits, vol. 22, No. 2, Apr. 1987, p. 255.
K. Kohiyama, et al., A Single-Chip Digital PLL System for TV Image Processing, ISSCC Digest of Technical Papers, Session 15, Video Signal Processors, Paper FP 15.1, Feb., 1991, p. 248.

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