Circuit for eliminating metastable events associated with a data

Details Circuit for eliminating metastable events associated with a data Circuit for eliminating metastable events associated with a data

1989-03-31

1991-07-30

Callahan, Timothy P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307480, 307269, 328109, 328 63, H03K 513, H03K 1900

Patent

active

050362216

ABSTRACT:
A circuit for reducing the metastable events produced by a data signal asynchronous to a system clock signal is provided. The circuit includes an edge detector (32) for detecting a transistion of the data signal. The edge detector (32) controls a clock disable/reenable circuit (46) which will disable a system clock directed to a clocked device (36). The period of disablement is the minimum setup time for the clocked device (36). After the minimum setup time has passed, the disable/reenable circuit (42) will reenable the system clock to the clocked device (36). The system clock may be modified by a duration limit circuit (68). Data directed to the clocked device (36) may be delayed via a delay circuit (70).

REFERENCES:
patent: 3979732 (1976-09-01), Hepworth et al.
patent: 4518865 (1985-05-01), Iwasaki
patent: 4694196 (1987-09-01), Hasley et al.
patent: 4789959 (1988-12-01), Hung et al.
patent: 4799023 (1989-01-01), Firooz et al.
patent: 4851710 (1989-07-01), Grivna

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