Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-08-03
2001-06-05
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C365S182000, C365S201000
Reexamination Certificate
active
06242936
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor integrated circuit devices, and more particularly to circuits for identifying defects that result in current leakage in such devices.
BACKGROUND OF THE INVENTION
Due to integrated circuit design and fabrication technologies, semiconductor integrated circuits continue to make generational improvements in operating speed, power consumption, and physical size. As just one example, each new generation of semiconductor memory devices has faster data access speeds, larger data storage capacity, and smaller overall physical sizes. Because most integrated circuit devices include a number of conductive layers that are separated from one another by insulating layers, one factor that has led to improvements in performance and size has been an increase in the number of conductive layers within the integrated circuit, as well as an increase in the density of the conductive lines that make up each conductive layer.
Unfortunately, despite the continuous advances in fabrication technology, there remain many uncontrollable factors in a semiconductor manufacturing process that can lead to product defects. Defects can arise from any of a number sources: very small particles, variation in starting materials, or lack of precision in a process step—such as an etching step, to name just a few. Due to the high density of conductive lines within highly integrated circuits devices, defects can lead to short circuit conditions (shorts) between adjacent conductive lines. Such shorts can be horizontal, undesirably connecting two conductive lines of the same conductive layer, or vertical, undesirably connecting lines from two different conductive layers.
Defects arising from manufacturing can be overcome by “repairing” an IC through the use of redundant circuits. A redundant circuit provides identical functionality to “standard” circuits in an IC. In the event a standard circuit is not operational due to a short, the standard circuit can be disabled, and replaced by a redundant circuit. In many types of semiconductor devices, the implementation of redundant circuits occurs at a manufacturing step referred to as “wafer probe.”
Wafer probe is performed while integrated circuit devices are one portion of a contiguous finished semiconductor wafer. The finished wafer is subsequently sliced into a number of individual die, each of which consists of a single integrated circuit device. During wafer probe, electrical probes are dropped onto individual devices to test the operation of the device. If a defect is located, it can be repaired via a “laser repair” step. During laser repair, a laser will evaporate a predetermined set of laser fusible links, and thereby replace a defective circuit with a redundant circuit. Each individual die will then be packaged by subsequent manufacturing steps.
While wafer probe and laser repair can increase yields by compensating for some manufacturing defects, there are still some defects that can be missed at wafer probe and result in defective devices. One type of defect that can escape detection at a conventional wafer probe step is a short circuit condition that initially draws only small amounts of current (a “slow leaker”). Such shorts can arise from very small holes in an insulating layer (“pin holes”) or very thin residual conductive filaments resulting from an inadequate etch step (“stringers”). Such defects, while drawing only a small amount of current at first, can degrade over time, drawing more current, eventually resulting in a failing device.
Certain reliability screening tests can catch pin hole and stringer defects. For example, integrated circuit devices are often subjected to a “burn-in” step or operational life (“op life”) step. Burn-in and op life steps exercise the functions of a device (sometimes under elevated temperatures and/or voltages) so as to induce failures. Burn-in and op life can screen out defective devices. Unfortunately, burn-in and op life are conducted on “finished” (i.e., fully packaged) devices. Finished devices, because they are covered by a package (such as an epoxy resin), cannot be repaired with a laser repair step. Thus, those defective devices identified at burn-in or op life must be scrapped.
It would be desirable to find some way of detecting slow leaker defects prior to an integrated circuit device being packaged. If detection of these types of defects were possible, devices that would otherwise be scrapped could be repaired, enhancing yield in a manufacturing process.
SUMMARY OF THE INVENTION
According to the preferred embodiment, a circuit is provided for driving a word line to select the word line. In addition, the circuit allows the word line to be tested for defects that result in relatively small amounts of current leakage. In a test operation, the preferred embodiment charges a word line and then electrically isolates the word line. The potential of the word line can then be monitored to determine if the word line suffers from current leakage. In the event there is current leakage from the word line, the potential will fall. If the word line does not suffer from current leakage, the potential will remain essentially the same.
In the preferred embodiment, the word line is selected by activating a charge circuit that includes an n-channel insulated gate field effect transistor (IGFET). The charge circuit couples a high voltage to a charge node, and the charge node is coupled to a word line. The operation of the charge circuit is controlled by the potential at a boot node. To prevent a threshold voltage drop caused by the n-channel IGFETs of the charge circuit, the charge circuit is enabled by driving the boot node to a boosted voltage. In a standard (non-test) cycle, the boot node is maintained at the boosted voltage, keeping the word line charged. In a test cycle, once the word line is charged, the boot node is discharged, thereby disabling the charge circuit and isolating the word line. The potential of the charge node can then be monitored to detect leakage.
According to one aspect of the preferred embodiment, a probe pad is coupled to the charge node, allowing the semiconductor memory device to be tested in wafer form.
According to another aspect of the preferred embodiment, the semiconductor memory device is a dynamic random access memory (DRAM), and the boot node is discharged in response to a sense amplifier enable signal.
An advantage of the preferred embodiment is that it can detect defects that result in slow current leakage.
Another advantage of the preferred embodiment is that semiconductor memory device can be tested in the wafer form, allowing defects to be repaired prior the device being packaged.
REFERENCES:
patent: 4831596 (1989-05-01), Tran
patent: 5117426 (1992-05-01), McAdams
patent: 5345422 (1994-09-01), Redwine
patent: 6038191 (2000-03-01), Fukuhara et al.
Ho Michael Duc
Le Duy-Loan T.
Smith Scott E.
Brady III Wade James
Holmbo Dwight N.
LeRoux E. P.
Metjahic Safet
Telecky , Jr. Frederick J.
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