Circuit for dividing the frequency of a digital clock signal by

Details Circuit for dividing the frequency of a digital clock signal by Circuit for dividing the frequency of a digital clock signal by

1988-12-05

1990-07-17

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

377108, 377107, H03K 2102, H03K 2138, H03K 2348

Patent

active

049425951

ABSTRACT:
A circuit for dividing a clock signal by two and one-half (2.5) is shown. The divide by two and one-half (2.5) circuit includes a clock selector circuit arranged to output a selected polarity of the first clock signal. A ring counter arranged to receive the clock selector circuit output signal, and output a signal that has a period of 3 times (3.times.) the signal received from the clock selector circuit. A divide by two circuit connected to the ring counter circuit and to the clock selector circuit. The divide by two circuit divides the ring counter output signal by two to produce an output signal. The divide by two output signal is then fed back to the clock selector circuit to regulate the selection of the first clock signal polarity, causing the ring counter to output a clock signal with a period of two and one-half times (2.5.times.) the first clock signal.

REFERENCES:
patent: 3614632 (1971-10-01), Leibowitz et al.
patent: 3896387 (1975-07-01), Kokado
patent: 4041403 (1977-08-01), Chiapparoli
patent: 4348640 (1982-09-01), Clendening
patent: 4390960 (1983-06-01), Yamashita et al.
patent: 4573176 (1986-02-01), Yeager
patent: 4646332 (1987-02-01), Sajor et al.

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