Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Signal transmission integrity or spurious noise override
Reexamination Certificate
1999-03-24
2001-06-19
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Signal transmission integrity or spurious noise override
C327S534000, C327S543000, C327S408000, C365S185250, C365S226000
Reexamination Certificate
active
06249172
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit for discharging to ground, with control of the discharge current, a node having a negative potential, to which a large capacitance is connected, particularly for use in a non volatile memory, such as a Flash EEPROM or EEPROM memory, in operations in which the initial conditions of the voltage values of the nodes are to be restored.
2. Discussion of the Related Art
Many conventional non volatile memory devices, especially those having a single voltage supply, need to internally generate voltage values out of the range between ground and the supply voltage. There exist therefore negative voltage levels and voltage levels higher than the supply voltage, which are essential for performing the operations of writing and erasing of the memory cells. The nodes of the circuit with negative voltage values, once said operations are terminated, must be restored to their initial voltage values.
For instance, making reference to
FIG. 1
, a Flash EEPROM memory is schematically represented.
FIG. 1
could as well represent a sector of a Flash EEPROM memory, in the case this includes more sectors selectively addressable. The memory comprises memory cells
1
, constituted by floating-gate N-channel MOS transistors, conventionally arranged in rows WLO-WLn (“word lines”) and columns BLO-BLm (“bit lines”) to form a matrix. The rows of the matrix are accessible through a row decoder ROW
13
DEC that receives and decodes row address signals RADD. Such decoder includes a plurality of final driving stages of the rows, each one substantially constituted by a CMOS inverter
2
supplied by a voltage VPCX and a voltage node RDS, to which a capacitance
3
is connected. Node RDS can be selectively connected to the ground of the integrated circuit in the case of reading and programming, as well as during erasing, if the particular sector must not be erased. To erase the sector, node RDS is instead connected to a line carrying a negative voltage value (V
N
), generated by a charge pump
4
. In this last case, the inputs of all the final inverters
2
are brought to the voltage VPCX.
The management of the negative voltage values in a circuit built in CMOS technology can pose some difficulties, in that it may not be possible to apply negative voltages of desired value to the source or drain electrodes of the N-channel MOSFETs, without forward biasing the source/substrate or drain/substrate junctions, since the substrate connects the integrated circuit to ground.
Such a problem is solved using CMOS technology that allows isolation of the bulk electrode of the N-chanTel MOSFET transistors from the substrate of the device which is necessarily connected to ground.
In
FIG. 2
, for instance, the section of an N-channel MOS transistor is shown, realized in a triple well technology, and in
FIG. 3
the circuit symbol that represents such transistor is shown. In
FIG. 2
a deep P type substrate
6
is connected to ground. An N type tub
7
formed inside the substrate
6
is connected to the supply voltage VDD; inside tub
7
, another P type tub
8
is formed with two N+ doped zones corresponding to the drain and source electrodes; the electrode of the tub
8
is connected to the source electrode. The substrate
6
and the tubs
7
and
8
are connected to the respective external electrodes thereof through contact regions that have a higher doping.
With this triple well technology the N-channel MOSFET has the N type tub
7
such that by applying the positive supply voltage VDD to this tub it is possible to reverse bias all the parasitic junctions existing inside the structure, even when negative voltages are applied to the source electrode, which is connected to the bulk electrode
8
of the transistor.
The way to discharge a node from a voltage value to another value having a small absolute value, provides for connecting the node to a node with constant potential value equal to the final value, through a transresistance. For instance, with reference to
FIG. 1
, switch means
5
are present that are closed between node RDS and the ground of the memory.
Such solution has the drawback that results in a transient whose duration depends, through an exponential relationship, on a time constant directly proportional to the value of the resistance R and of the capacitance C associated with the node that is to be discharged (&mgr;=R*C). When the capacitance associated with the node has a high value, the transient lasts for too long a time. Therefore, to speed up the process it is necessary to decrease the value of the discharge resistance, in such way to have a time constant of acceptable values.
However, by decreasing the value of the discharge resistance, the value of the current that flows through such resistance is increased and this creates undesired effects in the circuit:
a first effect is due to the fact that a high value current, injected in a node connected to a real (i.e., not ideal) voltage generator, whose internal impedance is therefore different from zero, can cause an undesired variation of the potential of this node; in the case such current is injected in reference nodes such as the ground and the supply voltage, malfunctions of the whole circuit can be caused;
a second undesired effect of the high values of current is the high dissipation of power for Joule effect, that can raise the operating temperature of the circuit component and reduce the reliability thereof;
a further complication derives from the fact that the cross-section of the conductors that form the electric connections inside the circuit have to be sized according to the maximum value of current density that can transit therethrough, to avoid phenomenons of electromigration, and a high value of the current requires therefore a large conductor cross-section, with a consequent increase of area and of parasitic capacitances.
In view of the state of the art described, it is an object of the present invention to provide a circuit capable of discharging to ground a node whose potential has negative values and to which a high capacitance is possibly associated, without incurring in the aforementioned problems.
SUMMARY OF THE INVENTION
According to the present invention, this and other objects are achieved through a circuit for discharging to ground and fed by a supply voltage, comprising a reference voltage, a node with negative potential, first circuit means for coupling the node with negative potential to the reference voltage in response to a control signal, and comprising second circuit means for determining, in the first circuit means, the passage of a controlled current for the discharge of the negative potential node.
REFERENCES:
patent: 5572152 (1996-11-01), Ueda
patent: 5610533 (1997-03-01), Arimoto et al.
patent: 5615146 (1997-03-01), Gotou
patent: 5617057 (1997-04-01), Rees et al.
patent: 5650959 (1997-07-01), Hayashi et al.
patent: 5736866 (1998-04-01), Harr
patent: 5767702 (1998-07-01), Hense et al.
patent: 5781035 (1998-07-01), Tashibu
patent: 5886937 (1999-03-01), Jang
Branchetti Maurizio
Commodaro Stefano
Ghilardelli Andrea
Mulatti Jacopo
Cunningham Terry D.
Galanthay Theodore E.
Morris James H.
STMicroelectronics S.r.l.
Wolf Greenfield & Sacks P.C.
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