Circuit for determining clock propagation delay in a...

Details Circuit for determining clock propagation delay in a... Circuit for determining clock propagation delay in a...

1998-04-10

2001-04-17

Luther, William (Department: 2664)

Pulse or digital communications

Cable systems and components

Transformer coupling

C375S356000, 37, C327S158000

Reexamination Certificate

active

06219384

ABSTRACT:

TECHNICAL FIELD
The invention relates to distribution of clock signals in digital circuits, and in particular to providing clock edges which define simultaneous timing events at destination digital subsystems.
BACKGROUND ART
There is a need for a clock source to provide simultaneous timing signals to a digital system. The timing signals are a series of timing events occurring at discrete and equal time intervals typically defined by a physical change in a voltage or current parameter. This physical change is frequently termed a “clock edge” and is usually associated with a rising and/or falling shift in the voltage or current level of a timing signal. The interval from the initiation of a first timing event to a second timing event is termed a “cycle”, and a signal comprising a series of timing event cycles is called a clock. The timing event typically originates from a single oscillator source and is distributed through a clock distribution apparatus to one or more subsystem components. The respective subsystem components then distribute the timing event to their constituent parts. The use of a clock in a digital system or more specifically a sequential digital system is well known and is described for example by Hill and Peterson, “Introduction to Switching Theory and Logic Design”, Third Edition, John Wiley and Sons, Inc., 1981, pp. 249-266, which is hereby incorporated by reference. Examples of binary logic circuits are discussed in Ibid. pp. 64-95.
The industry trend has been to minimize the time interval between successive timing events. This provides for a system that executes more tasks per unit time. Such a system is said to have a higher clock speed. A discussion of elements that limit the minimum time interval between successive timing events is given in Ibid. pp. 253-261. A digital system generally consists of multiple subsystem components, each containing sequential logic circuitry. These subsystem components exchange logic signals and are constituents of a larger digital system. As such, they require timing events from the same clock source. The timing events, clock edges, are signals that propagate at finite speed resulting in a time delay from the instant a timing event is initiated at a clock source to the instant it arrives at a subsystem component. Subsystem components cannot be located at the same physical point leading to the possibility that not all subsystem components will receive a timing event at the same time.
Generally, a subsystem component coordinates the initiation of a series of digital operations with the arrival of a timing event. If a clock system is such that timing events do not arrive at each subsystem component at the same time, then the difference in time between the arrival of timing events at different subsystem components is termed clock skew. Clock skew can prevent the various subsystem components from properly coordinating their operations with each other. To avoid possible logic errors resulting from clock skew between subsystem components, the time interval between consecutive timing events is increased to allow for the difference in propagation times between a clock source and the various subsystem components. Thus a system with negligible clock skew can operate at a higher clock speed than an otherwise identical system with clock skew.
With reference to
FIG. 1
, the path taken by a clock source
11
to a first subsystem component
10
is much shorter than the path taken to a second subsystem component
12
. As a result, the first subsystem component
10
will receive a timing event before the second subsystem component
12
by a time T
skew
. If the second subsystem component
12
responds to a first timing event by processing data and then sending the result to the first subsystem component
10
on logic lines
13
and the first subsystem component responds to a second timing event by latching in the information on logic lines
13
and processing it, clock skew would affect the performance of the entire system in the following manner. The time interval between consecutive timing events, T
cycle
, must be long enough to allow for data processing delay T
PD
1
at the first subsystem component
10
and data processing delay T
PD
2
at the second subsystem component
12
, allow time for the propagation of data T
p
on logic lines
13
, and allow time for a clock edge to propagate from the first subsystem component
10
to the second subsystem component
12
, T
skew
. In this case the minimum cycle time, T
cycle
, is given by:
T
cycle
>T
PD
1
+T
PD
2
+T
p
+T
skew
.  Eq. (1)
It is evident that the minimum cycle time is larger in a system with clock skew, T
skew
>0, than in a system without clock skew, T
skew
=0, by an amount equal to the clock skew. Therefore, to maximize the speed of a system, all of the subsystem components should receive the timing event, clock edge, simultaneously.
Historically, clock skew had not been an issue because the clock propagation time between subsystem components was a small fraction of the time interval between timing events. At present, however, logic systems with clock speeds exceeding 50 MHz are being used and the trend is for the clock speed to increase in future designs. In systems exceeding 50 MHz, the interval between timing events is less than 20 nanoseconds. In such systems, the time for a subsystem component to complete its task and communicate with another subsystem component is compromised significantly if the clock skew is 1 nsec or more. For example, the propagation speed of a clock signal on a typical printed circuit board using copper traces to route signals is approximately 6 inches per nanosecond. The size of a circuit board in a personal computer is commonly 9 inches by 9 inches, and the clock signals are routed via copper traces that are typically less than 12 inches long. On a 12 inch trace, a delay of 2 nsec will exist from the instant a timing event is initiated at a clock source to the time it arrives at the end of the trace. This 2 nsec delay is 10% of the allotted time interval between timing events in a 50 MHz system.
FIG. 2
illustrates the clock signal routing employed when a clock source
15
with a single output is used to distribute a clock signal to multiple digital subsystems
16
-
18
. The clock source
15
routes a clock edge signal to the destination digital subsystems
16
-
18
in a serial fashion, first to the first digital subsystem
16
, then to the second digital subsystem
17
, and finally to the third digital subsystem
18
. This results in a large clock skew between the first digital subsystem
16
and the third digital subsystem
18
.
FIG. 3
illustrates a first approach that is commonly used to minimize system clock skew. Clock distribution apparatus
20
creates multiple copies of a single clock, and routes separate copies of the clock to digital subsystems
21
-
24
. The time variations in the occurrence of the timing event at the different subsystem modules is reduced with respect to FIG.
2
.
A second approach, shown in
FIG. 4
, to improve the system speed is to add custom routing of multiple copies of a clock from a clock distribution apparatus
25
to each digital subsystem such that each trace
31
-
34
has an equal length from the clock distribution apparatus
25
to each digital subsystem
26
-
29
respectively. Equal trace lengths imply equal clock propagation delays and therefore no clock skew. This scheme allows the desired objective of having the timing events occur simultaneously at each subsystem. The disadvantage is that the clock traces must be custom routed, and sometimes this is physically difficult or impractical.
U.S. Pat. No. 4,998,262 describes a third approach to solving the clock distribution issue. The approach uses a simple single clock source with a dual daisy chain distribution scheme coupled with a receiver circuit at each digital subsystem that can regenerate or synthesize the required clock from the information available in the signal on the dual daisy chain. The inherent disadvantage

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