Computer graphics processing and selective visual display system – Display driving control circuitry – Adjusting display pixel size or pixels per given area
Reexamination Certificate
2001-02-13
2004-06-01
Eisen, Alexander (Department: 2674)
Computer graphics processing and selective visual display system
Display driving control circuitry
Adjusting display pixel size or pixels per given area
C345S204000, C345S213000
Reexamination Certificate
active
06744444
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a circuit for detecting a valid range of a video signal, which may be used in a display apparatus of a personal computer (PC) and the like.
Video signals utilized in PCs have signal formats of various numbers of scan lines, picture elements and frame frequencies. Further, a video signal has a valid range (a range of time during which the video signal is displayed on a display screen), which is located at various positions within the video signal. Accordingly, for purpose of providing an image display, it is required that a location that an input signal should occupy on a display screen be adjusted in accordance with the signal format of the input signal. Measures are taken to allow the valid range of the video signal to be detected automatically so that a portion of the video signal that is contained within the valid range may be displayed on a display screen at an appropriate position.
FIG. 11
is a block diagram showing a display apparatus using a conventional circuit for detecting a valid range of a video signal. In
FIG. 11
, a reference numeral
1
denotes an A/D converter which converts a video signal into a digital signal, and
2
denotes a PLL circuit which generates from a horizontal sync signal H
1
a dot clock and a horizontal reference signal, both of which are used in an internal processing. Further, a reference numeral
4
denotes an address generator which generates a horizontal address signal H
2
and a vertical address signal V
2
on the basis of the horizontal reference signal and a vertical sync signal V
1
, and
5
denotes a valid range detector which detects a valid range of a video signal. The address generator
4
and the valid range detector
5
form together a circuit
6
for detecting a valid range of a video signal. In
FIG. 11
, a reference numeral
7
denotes a display unit, which has a display screen and displays the video signal on the display screen in accordance with a horizontal address signal H
2
, a vertical address signal V
2
and an output signal from the valid range detector
5
. For ease of description, it is assumed in the description to follow that the display screen of the display unit
7
is a matrix display device having eight horizontal rows and four vertical columns or a total of 32 (=8×4) picture elements. The display screen may be any one of a liquid crystal panel, a PDP (plasma display panel) a DMD (digital micro-mirror device) and the like.
The operation of the conventional circuit shown in
FIG. 11
will be described below with reference to a series of timing charts shown in
FIGS. 12A
to
12
J.
FIGS. 12A and 12F
show a video signal S
1
which is input,
FIG. 12B
shows a vertical sync signal V
1
which is input,
FIGS. 12C and 12G
show a horizontal sync signal H
1
which is input,
FIGS. 12D and 12H
show a vertical address signal V
2
which is output from the address generator
4
,
FIGS. 12E and 12J
show a valid range detection flag signal F
1
which is used in the internal processing performed by the valid range detector
5
, and
FIG. 12I
shows a horizontal address signal H
2
.
FIGS. 12F
to
12
J show part of
FIGS. 12A
to
12
E in enlarged scale in time. In the description to follow, it is assumed that the horizontal sync signal H
1
and the vertical sync signal V
1
which are input are negative-polarity pulses, as shown in
FIGS. 12B and 12C
, respectively, having a falling edge as a Leading edge and a rising edge as a trailing edge.
The video signal S
1
shown in
FIGS. 12A and 12F
is input to the A/D converter
1
. The A/D converter
1
then converts it into a digital signal, which is sent to the valid range detector
5
and the display unit
7
.
The PLL circuit
2
produces a dot clock. The PLL circuit
2
produces a horizontal reference signal by frequency-dividing the dot clock, and controls the dot clock frequency so that the falling edge of the horizontal reference signal coincides with the falling edge of the horizontal sync signal H
1
shown in
FIGS. 12C and 12G
. The horizontal sync signal H
1
and the horizontal reference signal are generally substantially aligned in their falling edges, but the horizontal reference signal that is in complete synchronization with the dot clock is used in the internal processing.
The address generator
4
generates the vertical address signal V
2
by means of a counter which is reset by the falling edge of the vertical sync signal V
1
and which is incremented by one by the falling edge of the horizontal reference signal (which coincides with the falling edge of the horizontal sync signal H
1
), in a manner shown in FIG.
12
D. Simultaneously, the address generator
4
generates the horizontal address signal H
2
by means of a counter which is reset by the falling edge of the horizontal reference signal and which is incremented by one by the dot clock, in a manner shown in FIG.
12
I. The horizontal address signal H
2
and the vertical address signal V
2
are used by the valid range detector
5
and the display unit
7
as address information which indicates horizontal and vertical positions on the display screen.
The valid range detector
5
produces a valid range detection flag signal F
1
(see FIGS.
12
E and
12
J), which has a high level when the video signal S
1
is equal to or greater than a threshold TH and has a low level otherwise, on the basis of the comparison of the video signal S
1
shown in a solid line and a predetermined threshold TH shown in a broken line in
FIGS. 12A and 12F
. The threshold TH is chosen to be equal to about one-eighth of a maximum amplitude of the video signal S
1
. The valid range detector
5
outputs a minimum value (or “5” shown in
FIG. 12I
) and a maximum value (or “12” shown in
FIG. 12I
) of the horizontal address signal H
2
during the range of time the flag signal F
1
has the high level to the display unit
7
as a left-end coordinate and a right-end coordinate, respectively. It also outputs a minimum value (or “4” in
FIG. 12D
) and a maximum value (or “7” in
FIG. 12D
) of the vertical address signal V
2
during the range of time the flag signal F
1
has the high level to the display unit
7
as an upper-end coordinate and a lower-end coordinate, respectively.
The display unit
7
displays the video signal S
1
on the display screen at an appropriate position in accordance with left-end, right-end, upper-end and lower-end coordinates as input from the valid range detector
5
, and the horizontal address signal H
2
and the vertical address signal V
2
which are input from the address generator
4
. In the following description, values H and V of the horizontal address signal H
2
and the vertical address signal V
2
are denoted by (H,V) for purpose of convenience, wherein both H and V are positive integers.
By way of example, if the left-end coordinate is “5”, the right-end coordinate is “12”, the upper-end coordinate is “4” and the lower-end coordinate is “7”, the video signal which is input at a timing of (5,4) for the horizontal address signal H
2
and the vertical address signal V
2
is displayed on an upper-left picture element. The video signal which is input at a timing of (6,4) for the horizontal address signal H
2
and the vertical address signal V
2
will be displayed on a picture element which is located immediately to the right of the picture element, on which the video signal input at the timing of (5,4) has been displayed. A relationship between the position on the display screen and the values of the horizontal address signal H
2
and the vertical address signal V
2
is diagrammatically shown in FIG.
13
.
In the above-described operation of the valid range detector
5
, it is assumed that there is a video signal equal to or greater than the threshold at the left-end, right-end, upper-end and lower-end which collectively define the valid range, but this presents no problem for practical purposes inasmuch as a video signal is existing to the ends of the valid range of the video signal where an operating system having graphics use
Minami Kouji
Suzuki Yoshito
LandOfFree
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