Circuit for detecting the phase of received signal

Details Circuit for detecting the phase of received signal Circuit for detecting the phase of received signal

2000-01-21

2004-02-10

Bocure, Tesfaldet (Department: 2631)

Pulse or digital communications

Receivers

C375S331000, C375S365000

Reexamination Certificate

active

06690745

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a circuit for detecting the phase of a received signal and more particularly, to a circuit for detecting the phase of a received signal that is used in a receiver that receives a digitally modulated wave transmitted under a plurality of modulations with respective different C/N ratios that are required and which detects a phase angle of a received signal.
BACKGROUND ART
In a broadcast receiver that receives a digitally modulated wave applied with hierarchical transmission system in which a plurality of modulations with respective different C/N ratios that are required, for example 8PSK modulation, QPSK modulation and BPSK modulation, are combined in terms of timing and a digitally modulated wave under such modulations is repeatedly transmitted in successive frames, frame synchronizing signals are captured from demodulated base band signals (hereinafter referred to as symbol stream as well), a received signal phase rotation angle at the present time point is obtained from a signal point arrangement of the captured frame synchronizing signal, and the demodulated base band signals are subjected to opposite phase rotation based on the obtained received signal phase rotation angle, thereby making the demodulated base band signals coincide with the transmitted signal phase angle so as to be in absolute phase.
A conventional received signal phase detecting circuit, as shown in
FIG. 1
, comprises: a modulating circuit
1
; a frame synchronization detecting circuit
2
; and a frame synchronizing signal generator
3
; and in addition, delay circuits
41
and
42
constituting a block for detecting a received signal phase; a 0°/180° phase rotating circuit
43
; cumulative averaging circuits
45
and
46
; and a received signal phase determining circuit
47
that performs phase determination of a received signal under application of a conversion table using ROM. The frame synchronization detecting circuit
2
and the frame synchronizing signal generator
3
correspond to frame synchronizing signal capturing means for capturing a frame synchronizing signal from the demodulated base band signals and the delay circuits
41
and
42
correspond to extracting means for extracting symbol streams in the period of a frame synchronizing signal from the demodulated base band signals at the timing at which the symbol streams coincide with a bit stream of the synchronizing signal captured and reproduced by the frame synchronizing signal capturing means.
The conventional received signal phase detecting circuit shown in
FIG. 1
performs frequency conversion of a received digitally modulated wave to a predetermined intermediate frequency signal, supplies the intermediate frequency signal subjected to frequency conversion to the demodulating circuit
1
so as to demodulate and the demodulating circuit
1
sends out, for example, demodulated base band signals I(
8
) and Q(
8
) (hereinafter also referred to as base band signals I and Q, omitting the figures in each of the parentheses that indicates the number of bits together with the parentheses) of 8 bits that are quantized. The demodulated base band signals I(
8
) and Q(
8
) are also sent out to the frame synchronization detecting circuit
2
in order to capture a frame synchronizing signal, for example, that has been BPSK-modulated.
Description will here be made of mapping for each modulation method on the transmission side using FIGS.
2
(
a
) to (
c
). FIG.
2
(
a
) shows signal point arrangement in a case where 8PSK modulation is used as a modulation method. In the 8PSK modulation method, a digital signal of 3 bits (a, b, c) can be transmitted as 1 symbol, wherein combinations of bits that constitute 1 symbol are (0, 0, 0), (0, 0, 1), to (1, 1, 1), which are totaled in 8 ways. The digital signals each of 3 bits are converted to signal point arrangements
0
to
7
on the I-Q vector plane on the transmission side of FIG.
2
(
a
), which conversion is generally called as 8PSK mapping.
In the example shown in FIG.
2
(
a
), the bit sequence (0, 0, 0) is converted to a signal point arrangement “
0
”, a bit sequence (0, 0, 1) to a signal point arrangement “
1
”, a bit sequence (0, 1, 1) to a signal point arrangement “
2
”, a bit sequence (0, 1, 0) to a signal point arrangement “
3
”, a bit sequence (1, 0, 0) to a signal point arrangement “
4
”, a bit sequence (1, 0, 1) to a signal point arrangement “
5
”, a bit sequence (1, 1, 1) to a signal point arrangement “
6
”, and a bit sequence (1, 1, 0) to a signal arrangement “
7
”.
FIG.
2
(
b
) shows signal point arrangements in a case where QPSK modulation is used as a modulation method and in the QPSK modulation method, a digital signal of 2 bits (d, e) can be transmitted as 1 symbol, wherein combinations of bits constituting the symbol are totaled in 4 ways of (0, 0), (0, 1), (1, 0) and (1, 1). In the example of FIG.
2
(
b
), for example, a bit sequence (1, 1) is converted to “
1
”, a bit sequence (0, 1) to “
3
”, a bit sequence (0, 0) to “
5
”, and a bit sequence (1, 0) to “
7
”. It should be noted that a relation between a signal point arrangement and a arrangement number in each of other modulation methods is held in the same way as the relation in case of 8PSK modulation as a standard.
FIG.
2
(
c
) shows signal point arrangements in a case where BPSK modulation is used as a modulation method and in the BPSK modulation method, a digital signal (f) of 1 bit is transmitted as 1 symbol. Conversion of the digital signal (f) is such that, for example, (1) is converted to a signal point arrangement “
0
” and (0) is converted to a signal point arrangement “
4
”.
Now, description will be made of a frame synchronizing signal. In the hierarchical transmission system, a frame synchronizing signal is transmitted after being subjected to BPSK modulation with the lowest C/N ratio that is required. When arrangement is such that a bit stream of a frame synchronizing signal constituted of 16 bits is (S
0
, S
1
, . . . S
14
, S
15
), wherein the bit steam is sequentially sent out from S
0
, and a bit stream (0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, 1, 1, 1, 1, 0) or a bit sequence (0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1), the latter of which is the former sequence whose latter half 8 bits are inverted, are alternately sent out in successive frames. Hereinafter, the symbol stream of a frame synchronizing signal is also referred to as “SYNCPAT” or “nSYNCPA”T, the latter mark of which is the former symbol stream whose latter half 8 bits are inverted. The symbol streams are converted with BPSK mapping shown in FIG.
2
(
c
) on the transmission side to a signal point arrangement “
0
” or “
4
” and the converted symbol steam is transmitted.
When it is confirmed by a demodulated base band signal in the frame synchronization detecting circuit
2
that symbol streams of frame synchronizing signals “SYNCPAT” and “nSYNCPAT” that, as described above, are BPSK-mapped are alternately received in a repeating manner in constant frame intervals, it is judged that frame synchronization is established and a frame synchronization pulse is output in each frame period.
In a hierarchical transmission system in which normally, a plurality of modulation methods with respective different C/N ratios that are required are combined in terms of timing and a digitally modulated wave is repeatedly transmitted in successive frames, header data indicating the multiple combinations are multiplexed and a header data indicating the multiple combinations is extracted in response to a timing signal that is generated by a frame synchronizing pulse that is output from the frame synchronization detecting circuit
2
after it is judged that the frame Synchronization has been established. As a result, it is after a frame multiple combination is known that processings for different modulation types are separately enabled.
In other words, since the demodulating circuit
1
operates as an 8PSK demodulating circuit by the time when it is judged that frame synchronization has been established, the I and Q axes of the

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