Circuit for detecting synchronizing signal in frame synchronizat

Pulse or digital communications – Spread spectrum – Direct sequence

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375113, 3701051, 3701055, H04L 706, H04L 700, H04J 306

Patent

active

053675436

ABSTRACT:
A circuit for detecting a frame synchronizing signal and a circuit for detecting subframe synchronizing signals in the frame synchronization data transmission are presented. The former circuit generates a first signal which is at the logic 1 exclusively during the period that the frame synchronizing signal is received, and produces the logical product of the first signal and the data signal, the logical product corresponding to any error present in the frame synchronizing signal. In the latter circuit, a window pulse signal which corresponds to the bits of the subframes assigned to the subframe synchronizing signal is first produced, the bits of the data signal which are synchronous to the window pulse signal are next extracted, and an error bit is selected by excluding corrects bits from the extracted bits of the data signal. In this way an error bit in the synchronizing signal in the frame synchronization data transmission is detected.

REFERENCES:
patent: 3472961 (1969-10-01), Wheeler et al.
patent: 4247936 (1981-01-01), Hustig
patent: 4596981 (1986-06-01), Ueno et al.
patent: 4796282 (1989-01-01), Yoshida
patent: 4811366 (1989-03-01), Kage
patent: 5228037 (1993-07-01), Yonehara

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