Circuit for detecting plural kinds of multi-frame synchronizatio

Details Circuit for detecting plural kinds of multi-frame synchronizatio Circuit for detecting plural kinds of multi-frame synchronizatio

1987-10-14

1989-03-07

Pellinen, A. D.

Pulse or digital communications

Spread spectrum

Direct sequence

375108, 370105, 370108, H04L 700

Patent

active

048113670

ABSTRACT:
A system detects/recognizes multi-frame synchronization bits of concurrently existing plural unknown kinds of multi-frame synchronization in received signals of digital transmission. The above-mentioned detection as well as recognition is carried out by software in place of the wired logic of prior art. A micro processor instructs a gate to extract a specific bit out of received sequential bits. The extracted bit is input to a shift register and output therefrom after being delayed by the elapsing frame numbers via respective output terminals corresponding to the delaying frame numbers. The output bit is compared with non-delayed input bit, and if they meet a predetermined format, the bit is recognized as multi-frame synchronization. The bit extraction is scanned over all the control signal bits, and the results are stored in a memory. By use of thus stored information, the processor recognizes the existing types of multi-frame synchronization. Furthermore, based on thus stored information, the processor periodically monitors whether the synchronization is normal, and if it is stepping out, the synchronization detection procedure is repeated. Simplified circuits enable the flexible system to recognize mixed kinds of multi-frame synchronization. The benefit of eliminating hard-wired logic is obtained by programming of the micro processor.

REFERENCES:
patent: 4404675 (1983-09-01), Karcheuski
patent: 4493093 (1985-01-01), Veillard
patent: 4524445 (1985-06-01), Fujii

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