Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1981-01-15
1983-05-31
Heyman, John S.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
3072383, 3072386, 3072388, 307296R, 340662, 340663, H03K 1708
Patent
active
043862810
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention pertains to voltage detection and more particularly to the setting of a latch upon the loss of supply voltage to a circuit.
BACKGROUND OF THE INVENTION
Integrated circuits are being developed to provide a wide range of functions in telephone applications. One application of such integrated circuits is to store one or more telephone numbers and recall the selected number for transmission over the telephone line in place of the user manually entering the number. But with the types of integrated circuits most applicable for telephone functions the stored number can be lost if the power supply to the integrated circuit should drop to a low level. The power for the integrated circuit is typically not provided locally but is received over telephone lines from a central office. The power voltages received at the telephones are subject to wide variations in amplitude and occasionally there is a total loss of the power voltage.
If a number should be stored in the integrated circuit memory and then lost due to a voltage reduction or transient a meaningless number will be introduced into the memory. This would not be the number which was previously stored. Thus, there exists a need for a circuit which can detect the loss of voltage supplied to the integrated circuit such that the circuit can be cognizant of the validity of the number stored in memory and therefore will not read an erroneous number from memory.
SUMMARY OF THE INVENTION
In a selected embodiment of the present invention a circuit is provided for detecting a reduction in the supply voltage thereto. The supply voltage is provided to the circuit through first and second power terminals. A latch circuit having first and second states is connected to the first and second power terminals and is also connected to receive a reset signal from an external circuit. Circuitry is provided for driving the latch to the first state when the supply voltage becomes less than a preset amplitude. Further circuitry is provided for driving the latch to the second state upon receipt of the reset signal. Thus, the latch is set to the first state when the supply power has been lost and the data stored in a memory is incorrect. The latch is set to the second state by the external circuitry after the external circuitry has taken appropriate steps in response to the lost supply voltage.
BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings in which:
FIG. 1 is a schematic illustration of the circuit of the present invention; and
FIG. 2 is an illustration of waveforms which occur in the circuit of FIG. 1.
DETAILED DESCRIPTION OF THE INVENTION
The circuit of the present invention is illustrated as a schematic diagram in FIG. 1 and is generally designated by the reference numeral 10. A first power terminal 12 receives a supply voltage V+. A second power terminal 14 is connected to a supply voltage V.sub.M. In a typical embodiment the voltage supply V+ is at approximately 4.0 volts and the voltage supply V.sub.M is at 0.0 volts. However, these voltages can vary substantially without changing the operation of circuit 10. The supply voltage provided to circuit 10 comprises the difference in the voltages at terminals 12 and 14. This is illustrated as the waveform shown for terminal 12 in FIG. 2.
Terminal 12 is connected to the anode of a diode 16 which has the cathode thereof connected to a node 18. A P-type transistor 20 has the source terminal connected to node 18, the gate terminal connected to a node 22 and the drain terminal connected to a node 24. Another P-type transistor 26 has the source terminal connected to node 18, the gate terminal connected to a node 28 and the drain terminal connected to node 22.
A diode 30 has the anode terminal connected to node 28 and the cathode terminal connected to terminal 12. Two zener diodes 36 and 38 are connected serially between
REFERENCES:
patent: 3325684 (1967-06-01), Berger
patent: 4099068 (1978-07-01), Kobayashi et al.
patent: 4232236 (1980-11-01), Yomogida et al.
Heyman John S.
Mostek Corporation
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