Television – Camera – system and detail – Combined image signal generator and general image signal...
Reexamination Certificate
1997-11-05
2003-01-07
Vu, Ngoc-Yen (Department: 2612)
Television
Camera, system and detail
Combined image signal generator and general image signal...
C348S310000, C250S208100, C250S2140RC
Reexamination Certificate
active
06504572
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an integrated circuit design for CMOS imagers. More specifically, the present invention relates to methods and apparatus for early detection of fatal faults in CMOS imagers.
CMOS image sensors are now becoming competitive with charge coupled device (“CCD”) image sensors. Potential applications include digital cameras, night time driving displays for automobiles, and computer peripherals for document capture and visual communications.
Since the 1970s, CCD arrays have dominated the electronic image sensor market. They have outperformed CMOS array sensors in most important criteria including quantum efficiency, optical fill factor (the fraction of a pixel used for detection), charge transfer efficiency, readout rate, readout noise, and dynamic range. However, the steady improvement in CMOS technology (including increasingly small device size) has moved CMOS image sensors into a competitive posture. Further, in comparison to CCD technology, CMOS technology provides lower power consumption, increased functionality, and potentially lower cost. Researchers now envision single chip CMOS cameras having (a) integrated timing and control electronics, (b) a sensor array, (c) signal processing electronics, (d) an analog-to-digital converter, and (e) interface electronics. See Fossum, “CMOS Image Sensors: Electronic Camera On A Chip,” 1995 IEDM Technical Digest, Wash. DC, Dec. 10-13, 1995, pp. 17-25 which is incorporated herein by reference for all purposes.
CCD arrays are limited in that all image data is read by shifting analog charge packets from the CCD array interior to the periphery in a pixel-by-pixel manner. The pixels of the CCD array are not randomly addressable. In addition, due to voltage, capacitance, and process constraints, CCD arrays are not well suited to integration at the level possible in CMOS integrated circuits. Hence, any supplemental processing circuitry required for CCD sensors (e.g., memory for storing information related to the sensor) must generally be provided on separate chips. This, of course, increases the system's cost.
A persistent problem of both CMOS and CCD image sensor technologies is image degradation due to faulty pixels. Such faulty pixels arise from processing variations inherent in fabrication of numerous sensor chips. A pixel's fault may be manifested by an output indicative of a radiation exposure that does not accurately reflect the actual radiation exposure to which the pixel was exposed. For example, a pixel that outputs more charge than is expected to be accumulated upon exposure to a particular amount of radiation appears as a bright spot in an image. Similarly, a pixel that outputs less charge than expected appears as a dark spot.
Typically, image sensors are optically tested after fabrication to identify the number of faulty pixels that they contain. If any sensor has more than a specified number of faulty pixels, it must be rejected. Thus, sensor yield is limited by the number of faulty pixels typically produced on a chip. Not surprisingly, wide area sensors having large numbers of pixels have relatively low yields because they tend to have higher numbers of faulty pixels (the number of faulty pixels per total number of pixels is approximately constant for a given fabrication technology).
Existing test procedures rely on optical procedures in which each pixel is exposed to radiation of the same intensity and then “read” to determine whether the pixel output significantly deviates from an expected value. If so, the pixel is deemed “faulty.”Unfortunately, optical test procedures require fairly sophisticated equipment and can be difficult to conduct. Further, they may not accurately diagnose one type of particularly deleterious fault: the leaky access switch.
CMOS imagers include an array of pixels which are randomly addressable. Thus, each pixel is equipped with one or more access switches (usually MOS transistors) which allow independent access. For example in one array architecture, a pixel's output is read on a column line while all other pixels in that column are switched off. Unfortunately, the switch that controls the column access to a pixel (in such architecture) can leak. This has two detrimental effects. First, it causes the read-out from the pixel to be inaccurate (e.g., artificially low); some of the charge accumulated during exposure to radiation is leaked away before the pixel can be read. As a result, the pixel appears too dark in the resulting image. Second, and more seriously, the leaking charge finds its way onto the column line where it interferes with the output of every other pixel on the column. Hence, the leaky access switch corrupts not just the output of the pixel having the leaky switch, but the outputs of an entire pixel column or row. Typically, a CMOS imager having such leaky access switch must be discarded.
What is needed therefore is an improved image sensor design that can quickly and accurately identify CMOS image arrays containing a pixel with a leaky access switch.
SUMMARY OF THE INVENTION
The present invention provides a CMOS image sensor including circuitry for identifying leaky access switch type defective pixels. Preferably, the first test that a newly fabricated image sensor is subject to is an electronic test for leaky access switch pixels. This may be performed during electronic wafer sort (“ESW”). If such a leaky access switch is discovered, the imager is discarded without incurring further manufacturing cost. If, on the other hand, the imager is not found to contain a leaky access switch, it may packaged and then subjected to an optical test, or more expensive optical tests can be performed at the EWS level.
One aspect of the invention provides a particular method (implemented in a CMOS imager) for identifying a pixel having a leaky access switch. The method may be characterized as including the following sequence of events: (a) electronically setting a defined charge in a selected pixel of the CMOS imager; (b) reading the output of the selected pixel; and (c) comparing the output of the selected pixel to an expected value based upon the defined charge set in the selected pixel. If the output significantly deviates from the expected value, then the selected pixel is identified as having a leaky access switch. In this process, a delay should exist between when the charge is provided to the pixel and when that pixel's output is read. This allows ample time for the charge to escape from or enter into the pixel through the leaky access switch. The size of this delay should be roughly equal to the maximum expected exposure time of the sensor in use.
In general, the defined charge placed on the pixel must be an excess charge which will tend to escape over an output row or column line if the switch between the pixel and that line leaks. To adequately test for a leaky access switch, the defined charge set in the pixel may correspond to the pixel being exposed to a finite amount of radiation. That is, the charge set on the pixel will be equivalent to the amount of charge that would build up on the pixel when it is exposed to the defined intensity of radiation for a defined length of time. In the case where the pixel includes an n-well and a p-diffusion photodiode, excess holes are provided in the p-diffusion. Because the line connecting the pixel and a corresponding charge integrator is held at a low potential with respect to the diffusion, a leaky access switch will allow positive charge from the diffusion to leak onto the line.
For the test to be complete, the imager system will generally conduct steps (a) through (c) for all pixels in CMOS imager. Preferably, this full test is conducted prior to packaging the CMOS imager. If no pixels in the CMOS imager are found to include a leaky access switch, the system may conduct an optical test of the imager—possibly after packaging.
Another aspect of the invention provides a CMOS imager that may be characterized as including the following features: (a) one or more pixels capable of
Kramer Alan H.
Rambaldi Roberto
Tartagni Marco
Jorgenson Lisa K.
STMicroelectronics Inc.
Vu Ngoc-Yen
Weaver Jeffrey K.
LandOfFree
Circuit for detecting leaky access switches in CMOS imager... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit for detecting leaky access switches in CMOS imager..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit for detecting leaky access switches in CMOS imager... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3023574