Circuit for detecting false read data from EPROM

Details Circuit for detecting false read data from EPROM Circuit for detecting false read data from EPROM

1990-10-15

1992-09-15

Smith, Jerry

Excavating

365201, G06F 1100

Patent

active

051484366

ABSTRACT:
First and second EPROM transistors are coupled in series to a power source, a third EPROM transistor is connected in parallel with the series connection and a two input NAND gate has a first input connected to the junction between the first and second EPROM transistors by an inverter and a second input connected to the drain of the third transistor. The first and third transistors are programmed with the EPROM and the second transistor is not. When a read signal is applied to the gates of all three transistors a predetermined signal will be available at the output of the NAND gate if the EPROM read condition is not faulty.

REFERENCES:
patent: 4543647 (1985-09-01), Yoshida
patent: 4651304 (1987-03-01), Takata
patent: 4870618 (1989-09-01), Iwashita
patent: 4905191 (1990-02-01), Arai
patent: 4937787 (1990-06-01), Kobatake
patent: 4956816 (1990-09-01), Otsumi et al.

Affiliated with

Also associated with

Rating

Circuit for detecting false read data from EPROM does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit for detecting false read data from EPROM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit for detecting false read data from EPROM will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-742472