Circuit for decoding a diphase signal

Details Circuit for decoding a diphase signal Circuit for decoding a diphase signal

1979-07-17

1981-04-07

Segal, Robert

Demodulators

Amplitude modulation demodulator

Having specific distortion, noise or other interference...

360 43, 375 84, H03K 900

Patent

active

042609526

ABSTRACT:
Incoming diphase signals E which have base bit intervals delineated by spaced clocking signals with data information occurring between the clocking signals are fed to a four bit shift register 10 which in cooperation with an exclusive OR-gate 14 generates a pulse D for each diphase signal E transition. Upon receipt of a preamble comprising four diphase signal transitions, a shift register 16 provides a signal MSR which initiates the decoding of the following data information. A counter 24 stores counts related to the time intervals between each two successive clocking signals and counters 26 and 28 store a count related to an immediately subsequent time period which is three-fourths of the time interval. The occurrence of data information is sensed by a logic array 20 during successive time periods and a non-return to zero mark-space output signal K is stored in a flip-flop 22. The logic array 20 continually updates the counts stored by the counters 24, 26-28.

REFERENCES:
patent: 3737895 (1973-06-01), Cupp et al.
patent: 3859631 (1975-01-01), Holmes
patent: 3982195 (1976-09-01), Turner
patent: 4032915 (1977-06-01), Shanks et al.
patent: 4139870 (1979-02-01), Tachi
patent: 4167760 (1979-09-01), Decker
patent: 4184179 (1980-01-01), Deming

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