Coded data generation or conversion – Digital code to digital code converters – Serial to parallel
Patent
1987-10-29
1990-02-13
Miska, Vit W.
Coded data generation or conversion
Digital code to digital code converters
Serial to parallel
341101, H03K 1302
Patent
active
049010760
ABSTRACT:
A circuit for converting a multi-bit data signal from a first format to a second format. The circuit includes an input for receiving the multi-bit data signal in a first format, an output for providing the multi-bit data signal in a second format, and a ring counter having a number of stages for providing, in sequential order, stage output signals. A format conversion device connected between the input and the output has a number of latches with each latch being connected to the input for simultaneously receiving data bits of the multi-bit data signal in the first format. A control circuit is provided for controlling the latching of selected data bits in each of the latches, and a transmission circuit is provided between the latches and the output for transmitting the bits latched in the latches to the output responsive to the stage output signals of the ring counter, thereby placing the multi-bit data signal in the second format.
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IBM Technical Disclosure Bulletin, R. A. Schaadt, vol. 23, No. 2, Jul. 1980, "Shift Register Data Deserialization Without a Counter", pp. 516-517.
Askin Haluk O.
Ferraiolo Frank D.
Gonzalez Floyd A.
International Business Machines - Corporation
Miska Vit W.
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