Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-03-19
2002-02-05
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185260, C365S185270, C365S185290
Reexamination Certificate
active
06344995
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to flash-type non-volatile memory devices. More particularly, the present invention relates to a circuit for controlling a non-volatile memory cell and its control method.
2. Description of the Related Art
Non-volatile memory devices have been widely applied to commercial electronic products on account of programmability and data retention after power-off. Referring to
FIG. 1
, a split gate non-volatile memory cell
10
disclosed in U.S. Pat. No. 5,572,054 is shown in a cross-sectional view. The memory cell
10
is fabricated on a semiconductor substrate
12
, such as a P-type silicon substrate.
In
FIG. 1
, on the substrate
12
a source region
14
and a drain region
16
are defined with a channel region
18
therebteween. A first insulating layer
20
, for example, made of thermally-grown silicon oxide, is disposed over the drain region
16
, channel region
18
, and source region
14
. Disposed over the first insulating layer
20
is a floating gate
22
. The floating gate
22
is positioned over a portion of the channel region
18
and over a portion of the source region
14
. Preferably, the floating gate
22
can be a polysilicon gate. A second insulating layer
24
has a first portion
24
A disposed over the floating gate
22
and a second portion
24
B disposed adjacent to the sidewall of the floating gate
22
. For example, the second insulating layer
24
can be made of silicon oxide by oxidizing the surface of the floating gate
22
while the floating gate
22
is made of polysilicon. A control gate
26
has one portion
26
A disposed over the top wall portion
24
A of the second insulating layer
24
, and another portion
26
B is disposed over the first insulating layer
20
and is immediately adjacent to the sidewall portion
24
B of the second insulating layer
24
. Further referring to
FIG. 1
, the portion
26
B of the control gate
26
extends over a portion of the drain region
16
and over a portion of the channel region
18
.
The operation of the conventional non-volatile memory cell
10
is described as follows.
When it is desired to erase the cell
10
, a ground potential is applied to the source region
14
and to the drain region
16
. A positive voltage, on the order of about +15 volts, is applied to the control gate
26
. Therefore, charges on the floating gate
22
are induced through the Fowler-Nordheim tunneling mechanism to tunnel through the second insulating layer
24
to the control gate
26
, leaving the floating gate
22
positively charged.
When it is desired to program selective cell
10
, the ground potential is applied to the drain region
16
. A positive voltage level in the vicinity of the threshold voltage of the MOS structure defined by the control gate
26
(e.g., on the order of approximately of +1V volt) is applied to the control gate
26
. Another positive voltage on the order of about +13 volts is applied to the source region
14
. Therefore, electrons generated by the drain region
16
will flow from the drain region
16
towards the source region
14
through a weakly inverted channel region
18
. When the electrons reach the region where the control gate
26
meets the sidewall portion
24
B, the electrons see a steep potential drop approximately equal to the source voltage, across the surface region defined by the gap of the sidewall
24
B. The electrons will accelerate and become heated and some of them will be injected into and through the first insulating layer
20
onto the floating gate
22
, leaving the floating gate
22
negatively charged.
When it is desired to read memory cell
10
, the ground potential is applied to the source region
14
. A conventional read voltage, such as +5 volts, is applied to the drain region
16
and to the control gate
26
, respectively. If the floating gate
22
is positively charged, the entire channel region
18
directly beneath the floating gate
22
and the portion
26
B of the control gate
26
will be turned on to cause electrical current to flow from the source region
14
to the drain region
16
. This would be the logic “1” state. On the other hand, if the floating gate
22
is negatively charged, the channel region
18
directly beneath the floating gate
22
is either weakly turned on or is entirely shut off so that little or no current will flow through the channel region
18
directly beneath the floating gate
22
. In this manner, the cell
10
is defined to be programmed at the logic “0” state.
However, the current flowing through the insulating layer
20
or
24
during the program or erase operation may build a voltage potential which is linearly proportional to the logarithmic scale of the time of current-flowing. After several erase-program cycles, the number of charges to be stored in the floating gate
22
declines gradually so as to decrease the current flowing between the source region
14
and the drain region
16
at the logic “1” state. Even worse, it can become a difficult task to identify between the logic “1” state and the logic “0” state.
Increasing the erase voltage may be a feasible approach to resolve the aforementioned problem without modifying structure of the memory cell
10
itself. However, the maximum value of the erase voltage is limited by the junction breakdown effect, and thus it can not be sufficiently increased to enhance the erase performance.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a circuit for controlling a non-volatile memory cell and its control method to enhance the erase performance without modifying the memory cell itself.
The above objects can be realized by providing a circuit for controlling a non-volatile memory cell having a source, a drain, a control gate, and a bulk. The control circuit comprises a voltage source, a first charge-pumping circuit, a word-line switch, a second charge-pumping circuit, a source switch, a third charge-pumping circuit, and a bulk switch. The first charge-pumping circuit, second charge-pumping circuit and third charge-pumping circuit respectively generate a first positive voltage, second positive voltage and negative voltage in response to the voltage source. The word-line switch selects and applies one of the voltage source or the first positive voltage to the control gate. The source switch selects and applies one of a ground potential or the second positive voltage to the source. The bulk switch selects and applies one of the ground potential or the negative voltage to the bulk.
During an erase operation the first positive voltage is applied to the control gate and the negative voltage is applied to the bulk. Accordingly, the potential difference between the substrate and the control gate can be raised to increase the number of charges to be stored in the floating gate even after long-term erase-program cycles.
REFERENCES:
patent: 5406521 (1995-04-01), Hara
patent: 5572054 (1996-11-01), Wang et al.
patent: 5894438 (1999-04-01), Yang et al.
patent: 5898606 (1999-04-01), Kobayashi et al.
patent: 5943267 (1999-08-01), Sekariapuram et al.
patent: 6005809 (1999-12-01), Sung et al.
Chen Wei-Fan
Yu Ta-Lee
Ho Hoai V.
Nath&Associates PLLC
Novick Harold L.
Winbond Electronics Corp.
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