Circuit for controlling setup/hold time of semiconductor device

Details Circuit for controlling setup/hold time of semiconductor device Circuit for controlling setup/hold time of semiconductor device

1999-12-30

2001-05-15

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S270000, C327S376000

Reexamination Certificate

active

06232811

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, specifically, to a circuit for controlling the setup/hold time of a semiconductor device, which sufficiently secures the margin of setup/hold time in clock latching operation.
2. Discussion of Related Art
When a clock is changed from a low level to a high level in a semiconductor device, the left side of the point of time when the clock is changed is generally called a setup time and its right side is called a hold time. A delay occurs in the reference clock being inputted to the semiconductor device due to various external causes, generating an internal clock K_int. The margin of one of the setup time and hold time is biased according to an input signal having a delay on the basis of the internal clock, decreasing the margin of one of the setup time and hold time.
A conventional semiconductor device control signal input circuit is explained below with reference to the attached drawings.
FIG. 1
shows the configuration of the conventional semiconductor device control signal input circuit, and
FIG. 2
shows the operation waveforms of the circuit of FIG.
1
. The control signal input circuit includes a plurality of input pads through which an external clock signal clock_pad and external command signal command_pad are supplied into a semiconductor device, and a plurality of buffers for generating an inner clock signal clock_i and inner command signal command_i according to the external clock signal_pad and external command signal command_pad. Each of the buffers consists of four-stage buffers having different capacities. Here, the final-stage buffer a
4
is configured of a buffer having a large driving power because the inner clock signal is used in the semiconductor device most frequently so that intensive load is applied to the buffers. The first buffers a
1
, a
2
, a
3
and a
4
, serially connected, generate the inner clock signal, and second buffers b
1
, b
2
, b
3
and b
4
, serially connected, generate the inner command signal.
As shown in
FIG. 1
, the buffers generating the inner command signal are configured of buffers having medium capacities because they do not require large capacity compared to the buffers generating the inner clock signal. The delay times of buffers connected to the clock signal input pad and command signal input pad are synchronized with each other, and the phase difference between the inner clock signal clock_i and inner command signal command_i is set to 180°, thereby making the periods of setup time and hold time symmetrical to each other. In the conventional control signal input circuit constructed as above, clock signal clock_pad and command signal command_pad are applied to the input pads, and pass through buffering process, to be used inside the semiconductor device.
After passing through the buffers, clock signal clock_pad and command signal command_pad pass through a clock buffer delay and command buffer delay, respectively, to be converted into the inner clock signal clock_i and inner command signal command_i. If the buffer delays are identically designed in the normal state to allow the input signal to have the phase of 180°, the center of the inner command signal command_i accords with the falling edge of the inner clock signal clock_i, which latches inner data of the semiconductor device, making the margins of the setup time and hold time identical to each other. As shown in
FIG. 2
, the center of the clock signal externally applied must be placed between the clock signal and command signal when latch is carried out between clocks. This requires sufficient margin of setup/hold time.
The aforementioned conventional control signal input circuit has the following problems. Though the clock buffer delay and command buffer delay are constructed to be operated identically in the normal condition, the operation margins of them are different from each other, as shown in
FIG. 3A
, due to a change in characteristics of PMOS transistors and NMOS transistors and temperature variation caused by variation in their fabrication process. This may result in the decrease in margin of one of the setup time tSETUP and hold time tHOLD.
FIG. 3A
shows that the setup time is in discord with the hold time when the clock buffer delay becomes longer than the command buffer delay due to variation in the characteristics of the transistors.
Meanwhile, when input clock signal clock_pad and input command signal command_pad, externally applied to the semiconductor device, do not have the phase difference of 180° therebetween even though the clock buffer delay and command buffer delay have the same operation margin, as shown in
FIG. 3B
, the setup/hold times of inner clock signal clock_i and inner command signal command_i become different from each other.
FIG. 3B
shows that there is disagreement of inner signals clock_i and command_i when the setup time is in discord with the hold time in external signals clock_pad and command_pad, in which tSETUP_pad<tHOLD_pad means the disagreement of the inner signals.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a circuit for controlling the setup/hold time of a semiconductor device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a circuit for controlling the setup/hold time of a semiconductor device, which sufficiently secures the margin of the setup/hold time in clock latch operation.
To accomplish the object of the present invention, there is provided a circuit for controlling the setup/hold time of a semiconductor device, including: a setup/hold on signal generator for generating a setup/hold on signal of the semiconductor device; a comparison signal generator for converting the difference between pulse widths of the setup on signal and hold on signal of the setup/hold on signal generator into the voltage difference across an inner capacitor, to generate a comparison signal for the setup/hold time; a comparison signal detector for detecting the comparison signal generated by the comparison signal generator and amplifying it to a predetermined level; a clock delay path selection signal generator for generating a clock delay path selection signal according to the level of the signal detected by the comparison signal detector; and a clock/command signal processor for outputting a clock signal and command signal applied to input pads as an inner clock signal and inner command signal whose delays are compensated according to the clock delay path selection signal.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 4256974 (1981-03-01), Padgett et al.
patent: 6127869 (2000-10-01), Hirasaka

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