Circuit for controlling external bipolar buffers from an MOS per

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G06F 300, G06F 922, G06F 1342

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045946540

ABSTRACT:
A circuit for controls external bipolar buffers for an MOS peripheral device capable of operating in master end slave modes. The circuit provides for a slave mode logic block and a master mode logic block for generating a DATA TRANSMIT ENABLE SIGNAL to permit the bipolar buffer to transmit data signals from the peripheral device to a system bus. The circuit also provides for a second slave mode logic block and a master mode logic block for generating a DATA RECEIVE ENABLE block to permit the bipolar buffer to transmit data signals from the system bus to the peripheral device. Each slave mode logic block is responsive to condiion signals, such as CHIP SELECT and READ/WRITE. Each master mode logic block is responsive to timing signals and signals generated internally within the periphel device so that the master mode DATA RECEIVE and DATA TRANSMIT signals occur only in predetermined timing cycles.

REFERENCES:
patent: 3374465 (1968-03-01), Richmond et al.
patent: 4047201 (1977-09-01), Kerllenevich
patent: 4200916 (1980-04-01), Seipp
patent: 4319338 (1982-03-01), Grudowski et al.
patent: 4453229 (1984-06-01), Schaire
patent: 4528626 (1985-07-01), Dean et al.

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