Circuit for controlling data output

Details Circuit for controlling data output Circuit for controlling data output

2007-06-29

2009-11-10

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S141000, C327S142000, C327S002000, C327S047000

Reexamination Certificate

active

07616034

ABSTRACT:
Disclosed is a data output control circuit for controlling data output. The data output control circuit includes a delay lock loop for outputting a first clock by delaying an external clock in response to a control signal, a phase detector for outputting a detection signal by detecting a frequency of the external clock in response to the control signal, a decoder for outputting a selection signal by decoding the detection signal, and a delay unit for outputting a second clock by delaying the first clock or inverting and delaying a phase of the first clock in response to the selection signal.

REFERENCES:
patent: 6404248 (2002-06-01), Yoneda
patent: 7405996 (2008-07-01), Minzoni et al.
patent: 2005/0174155 (2005-08-01), Heightley et al.
patent: 2007/0152715 (2007-07-01), Park
patent: 1020040021478 (2004-03-01), None
patent: 1020050105557 (2005-11-01), None
patent: 1020060056550 (2006-05-01), None
Notice of Patent Grant mailed Jan. 8, 2008 for the corresponding KR10-2006-0059802.

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