Circuit for controlling a power MOS transistor and detecting...

Details Circuit for controlling a power MOS transistor and detecting... Circuit for controlling a power MOS transistor and detecting...

2000-07-19

2002-11-19

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Utilizing three or more electrode solid-state device

C327S427000, C327S435000

Reexamination Certificate

active

06483370

ABSTRACT:

TECHNICAL FIELD
The present invention relates to circuits integrating a power MOS transistor with its control circuit, and more particularly to a control circuit with load detection for a high-frequency switching power MOS transistor.
BACKGROUND OF THE INVENTION
FIG. 1
very schematically shows a conventional example of an integrated circuit of the type to which the present relates. Integrated circuit
1
essentially includes a power MOS transistor
2
, the drain d and the source s of which define terminals, respectively
3
and
4
of the integrated circuit in communication with the outside. Terminal
3
corresponds to a terminal on which a voltage for supplying the load controlled by circuit
1
is applied. Terminal
4
corresponds to an output terminal intended for connection to a first terminal of the load to be controlled, the other terminal of the load being generally grounded. Transistor
2
is controlled by a circuit
5
(CTRL), an output terminal of which is connected to gate g of transistor
2
. Circuit
5
generally includes several input terminals (symbolized by a multiple-wire connection
6
) and/or terminals for parameterizing the circuit operation.
Most often, in the use of a circuit
1
such as illustrated in
FIG. 1
, it is also desired to detect the presence of the load in the circuit. For this purpose, circuit
1
further includes a terminal
7
intended for providing the result of a load presence detection performed within circuit
1
by a block
8
(DET).
FIG. 2
shows, in the form of block diagrams, an example of assembly of an integrated circuit
1
such as illustrated in
FIG. 1
to control a load
10
(Q). Load
10
is series-connected with transistor
2
(not shown in
FIG. 2
) of circuit
1
, that is, terminal
3
is connected to a positive supply terminal for application of a voltage Vbat, and terminal
4
is connected to a first terminal of load
10
, a second terminal of which is connected to ground m. In the example of
FIG. 2
, the assembly provides the function of detecting the presence of the load between terminals
4
and m. The present invention more specifically applies to the load detection and, more precisely, to the detection of the presence of the unsupplied load (that is, with transistor
2
in the off state).
To detect the presence of a load
10
in the assembly while said load is not supplied, a resistor Rp is provided in parallel with transistor
2
. In other words, resistor Rp is connected, most often externally to circuit
1
, between terminals
3
and
4
. With such an assembly, if the load is present, terminal
4
is at a potential corresponding to the ground when transistor
2
is on. If the load is absent, that is, terminal
4
is floating, this terminal is at a positive potential, here potential Vbat, minus the voltage drop in resistor Rp. The value of resistor Rp generally is several kilo-ohms to avoid generating too high a consumption or strongly dissipating.
Generally, and especially if the value of voltage Vbat is different from the low supply voltage of detection circuit
8
, resistor Rp is connected between terminal
4
and a terminal (not shown) of application of a biasing voltage Vpol (for example, 5 volts).
Exploiting the measurement of the voltage on terminal
4
by resistor Rp raises several problems.
A first problem is due to the switching time of transistor
2
. This problem is illustrated by
FIG. 3A
, which shows in the form of a timing diagram an example of the shape of the output voltage V
4
of circuit
1
for supplying a load Q.
This example relates to a turn-on control at a time t
0
that translates as a voltage V
4
reaching voltage level Vbat (neglecting the series voltage drop in transistor
2
in the on state) at a time t
1
. The difference between times t
0
and t
1
represents the turn-on switching time of transistor
2
. In the example of
FIG. 3A
, it is assumed that at a time t
2
, circuit
5
turns off transistor
2
. This turn-off control translates, from a time t
3
, as a decrease of voltage V
4
until said voltage is annulled at a time t
4
. The time interval between times t
2
and t
3
corresponds to the response time (tdoff) of the transistor, that is, the delay of its switching with respect to the received control signal. The time interval between times t
3
and t
4
corresponds to the off time of the transistor (tf), generally given as being the time of decrease of the voltage on terminal
4
from 90% to 10% of voltage Vbat.
The detection of the presence of a load in series with transistor
2
can, in the off state, be polluted by the off switching time of the transistor. Indeed, in exploiting the measurement of the potential of source s of transistor
2
between times t
2
and t
4
, the absence of a load will be detected, even if said load is present. This is due to the fact that the off state of the transistor is detected from time t
2
when the control circuit has sent the turnoff order, but that the disappearing of the potential on terminal
4
when a load is present only occurs at the end of the switching time.
Accordingly, the exploitation of the measurement has to be delayed with respect to time t
2
of the turn-off control. This delay is most often performed by a capacitive filter. The filtering time must then be adapted to the transistor switching time.
Another problem that is raised in exploiting this voltage detection to determine the presence or the absence of a load while the circuit is off is that the transistor switching time depends on supply voltage Vbat of the assembly. Accordingly, a filtering time corresponding to the worst possible case of the assembly has to be provided. This situation is illustrated in
FIG. 3B
that illustrates, in the form of timing diagrams, the shape of a signal for controlling the exploitation of the measurement. This signal illustrates the necessary filtering delay. In the example of
FIGS. 3A and 3B
, it is assumed that as long as control signal Vf illustrated in
FIG. 3B
is high, the reading of the measurement voltage cannot be performed. Accordingly, this signal is high during the entire period (t
0
-t
2
) when the transistor is on, since the presence of the load is then detected by other means (current measurement), and between time t
2
and a time t
5
representing the necessary filtering delay after the transistor turn-off order. As illustrated in
FIG. 3B
, it is generally necessary, to guarantee a proper detection, to take a filtering delay (t
2
-t
5
) greater than the minimum filtering delay (times t
2
to t
6
) itself corresponding to the worst off switching case of transistor
2
(illustrated by the dotted lines in FIG.
3
A).
All these precautions often result in extended filtering times that, in some applications, even prevent the detection of the absence of a load. Such is the case, for example, if integrated circuit
1
is used to control transistor
2
at frequencies on the order of one kilohertz, which is a usual value in pulse-width modulation applications (PWM). In such applications, the absence of a load can then no longer be detected since the security margin to be taken on the filtering delay is not negligible, or may even exceed the period of the signal controlling the transistor to the on state.
SUMMARY OF THE INVENTION
The disclosed embodiments of the present invention provide a novel circuit for detecting the presence of a load that overcomes the disadvantages of known circuits and enables reliable detection of the presence of a load.
While a first solution would be to reduce the switching time of the circuit power transistor, such a solution would not be fully satisfactory, since reducing the switching time of a power MOS transistor inevitably results in increasing the switching noise. Accordingly, this solution generates a noise problem, which is most often not desirable.
The present invention thus also provides a solution that is compatible with the other circuit operation requirements and, in particular, with a need for low switching noise.
The present invention provides reducing the filtering time to the smalles

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