Circuit for controllable generation of pseudoerrors in bit proce

Details Circuit for controllable generation of pseudoerrors in bit proce Circuit for controllable generation of pseudoerrors in bit proce

1983-09-30

1986-05-06

Atkinson, Charles E.

Excavating

307358, G06F 1100

Patent

active

045876533

ABSTRACT:
A circuit for generating pseudoerrors when the value of a received digital bit signal enters a pseudoerror region, as may be employed in the control loop of an adaptive system. The circuit includes its own feedback to control the boundaries of the pseudoerror region so that the rate of pseudoerror generation lies within a useful range.

REFERENCES:
patent: 3214700 (1965-10-01), Hook
patent: 3638138 (1972-01-01), Progler et al.
patent: 4034340 (1977-07-01), Sant'Agustino
patent: 4305150 (1981-12-01), Richmond et al.
patent: 4375099 (1983-02-01), Waters et al.

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