Circuit for confirming a connection route of address control mem

Details Circuit for confirming a connection route of address control mem Circuit for confirming a connection route of address control mem

1994-03-03

1995-07-18

Hsu, Alpus

Multiplex communications

Wide area network

Packet switching

370 68, H04Q 1104

Patent

active

054348579

ABSTRACT:
A circuit for confirming a connection route of an address control memory includes a data memory, an address counter and the address control memory. The address control memory includes a reading memory for storing data to an address which is a respective position of the time-division multiplexed data in time slots given when the time-division multiplexed data is read from the data memory as an output data and the data is a respective position of the time-division data in the time slots given when the time-division multiplexed data is written into the data memory as input data. A writing memory is provided for storing data to an address which is a respective position of the time-division multiplexed data in time slots given when the time-division multiplexed data is written to the data memory as input data, and the data is a respective position of the time-division multiplexed data in time slots given when the time-division multiplexed data is read from the data memory, thereby specifying from the time slot position of data at the time of reading, the time slot position of data at the time of writing, and specifying from the time slot position of data at the time of writing, the time slot position of data at the time of reading.

REFERENCES:
patent: 3956593 (1976-05-01), Collins et al.
patent: 4470139 (1984-09-01), Munter
patent: 4759012 (1988-07-01), Suzuki
patent: 4941141 (1990-07-01), Hayano
patent: 5040174 (1991-08-01), Takeuchi et al.
patent: 5123012 (1992-06-01), Suzuki et al.

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