Circuit for compressing digital images while retaining image fid

Image analysis – Histogram processing – For setting a threshold

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358426, G06K 936

Patent

active

053116020

ABSTRACT:
An image compressing circuit is comprised of: a number generating circuit which generates a respective number for each X-bit pixel in an input image such that the respective number changes in a cyclic fashion from pixel to pixel across each row of pixels in the input image; and, a translator circuit which performs a translation on each individual X-bit pixel together with its respective number to produce a corresponding Y-bit pixel, where Y is less than X. This translation is one which, when performed sequentially on several consecutive X-bit pixels of a single magnitude and their respective numbers for one cycle of the numbers, produces a series of Y-bit pixels of one or two magnitudes with an average value that increases monotonically as the single magnitude increases. By these Y-bit pixel series, the fidelity of the input image is retained even though Y is less then X.

REFERENCES:
patent: 4245258 (1981-01-01), Holladay
patent: 4866533 (1989-09-01), Nagashima
patent: 5070532 (1991-12-01), Faul et al.
patent: 5111194 (1992-05-01), Oneda
patent: 5175807 (1992-12-01), Cawley et al.

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