Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Patent
1997-12-04
1999-11-23
Tran, Toan
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
327 77, 327 53, H03K 5153
Patent
active
059907096
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The job of comparing two electrical quantities to one another occurs in many fields of technology. For example, these comparisons are thus a foundation of electrical mensuration technology. Threshold equations can also be technically realized with the assistance of evaluator circuits.
Methods that compare electrical quantities with the assistance of operational amplifiers are known and are often employed (U. Tietze, Ch. Schenk, Halbleiterschaltungstechnik, 9th Edition Springer Verlag, 1990, pages 132 through 143). A significant disadvantage of these methods is comprised in the conversion of static dissipated power and in the comparatively large space requirement of such circuits, particularly when a great number of them are required. A further possibility of implementing an evaluation of two electrical quantities is comprised in the employment of a neuron MOS inverter, whereby the reference quantity to which another electrical quantity is to be compared is determined by the switching threshold of the neuron MOS inverter (T. Shibata and T. Ohmi, "A function MOS Transistor featuring gate-level weighted sum and threshold operations", IEEE Trans. Electron Devices, 39, 1992, pages 1444-1455). The employment of a neuron MOS inverter in this context exhibits a number of disadvantages. A static quadrature-access current component for all potentials flows on the floating gate .phi..sub.F with V.sub.SS +V.sub.th,n <.phi..sub.F <V.sub.DD -V.sub.th,p, this corresponding to the normal case during operation as threshold gate. Moreover, it is necessary to govern the technology parameters extremely well, so that the threshold dimensioning corresponds to the desired behavior, i.e. that narrow tolerances of the threshold voltage must be adhered to.
European reference EP 0 497 319 A1 discloses a circuit arrangement for the comparison of two electrical quantities that comprises a current mirror, two MOS field effect transistors as well as an inverter unit. The currents supplied by the two transistors are compared to one another in the current mirror and the result signal is offered at the output of the inverter unit. This circuit arrangement only makes a comparison of two electrical quantities possible.
Fundamentals about the neuron MOS field effect transistor are known from T. Shibata, A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations, IEEE Transactions on Electron Devices, Vol. 39, No. 6, New York, pp. 1144-1455, June 1992.
U.S. Pat. No. 3,850,635 discloses a multiplier cell containing two comparators.
SUMMARY OF THE INVENTION
The invention is based on the problem of comparing an electrical quantity that is made available by a neuron MOS field effect transistor to a reference quantity.
In general terms the present invention is a circuit arrangement for the comparison of two electrical quantities that are made available by a first neuron MOS field effect transistor and a reference transistor. A current mirror is provided. An output of the first neuron MOS field effect transistor is coupled via a first terminal to an output of the current mirror, and an output of the reference transistor is coupled to an input of the current mirror. The first terminal is connected to at least one terminal of an inverter unit at whose output a result signal of the comparison pends.
Advantageous developments of the present invention are as follows.
A first switch unit is provided that is connected to the first terminal and to the control terminal of the inverter unit.
A second switch unit is provided, whereby a first terminal of the second switch unit is connected via a second terminal to an input of the first neuron MOS field effect transistor and to an input of the reference transistor.
The reference transistor is formed by a second neuron MOS field effect transistor.
The reference transistor is formed by an MOS field effect transistor.
The first switch unit and the second switch unit is composed of an MOS field effect transistor.
The first switch unit or the second sw
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IEEE Transactions on Electron Devices, vol. 39, No. 6, Jun. 1992, XPO00271791, T. Shibata et al, A Functional MOS Transistor Featuring Gate-Level Weighted Sum & Threshold Operations, pp. 1444-1455.
IEEE Transactions on Electron Devices, vol. 40, No. 5, May 1993, XPO00364271, T. Shibata et al, Neuron MOS Binary-Logic Integrated Circuits, Part II: Simplifying Techniques of Circuit Configuration and their Practical Applications, pp. 974-979.
IEICE Transactions on Fundamentals of Electronics, Communica- tions & Computer Sciences, vol. E75-A, No. 7, Jul. 1992, K. Tsukano et al, A New CMOS Neuron Circuit Based on a Cross-Coupled Current Comparator Structure, pp. 937-943.
ALTA Frequenza, vol. XXXXVIII, No. 11, Nov. 1969, D. Ferrari et al, Some New Schemes for Parallel Multipliers, pp. 843-852.
U. Tietze, Ch. Schenk, Halbleiterschaltungstechnik, 9 Auflage, Springer-Verlag, 1990, pp. 132-143.
Prange Stefan
Thewes Roland
Weber Werner
Wohlrab Erdmute
Siemens Aktiengesellschaft
Tran Toan
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