Circuit for combining delta modulated signals

Details Circuit for combining delta modulated signals Circuit for combining delta modulated signals

1980-08-28

1982-04-13

Safourek, Benedict V.

Pulse or digital communications

Repeaters

Testing

179 1CN, 179 18BC, 340347C, 370 62, H04M 356

Patent

active

043251390

ABSTRACT:
A circuit for combining a plurality of delta modulated speech signals, each signal being represented by a stream of input bits. Once each clock cycle, a multiplexer (101) sequentially applies one bit from each of the streams to an up-down counter (103) to either increment or decrement a count contained therein. The state of the most significant bit position of the up-down counter is then stored in a D-type flip-flop (104). A feedback bit assumes the inverse state of the stored most significant bit position and is sequentially applied under the control of a binary counter (102) to the up-down counter along with a bit from each of the streams during the next clock cycle. An output bit assumes the state of the stored most significant bit position, and an output signal consisting of a plurality of output bits from successive clock cycles represents the approximate linear sum of the delta modulated speech signals. The application of the feedback bit to the up-down counter can be controlled by the binary counter so that the output signal can represent either a reduced or an amplified linear sum of the delta modulated speech signals.

REFERENCES:
patent: 3980953 (1976-09-01), Nance et al.
patent: 4006475 (1977-02-01), Candy et al.
patent: 4162376 (1979-07-01), Hirschmann
patent: 4215247 (1980-07-01), Lambert

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