Television – Image signal processing circuitry specific to television – Dc insertion
Reexamination Certificate
1998-11-30
2001-03-20
Hsia, Sherrie (Department: 2614)
Television
Image signal processing circuitry specific to television
Dc insertion
C348S695000, C348S697000
Reexamination Certificate
active
06204892
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a clamping circuit and, more particularly to a pedestal clamping circuit for clamping a pedestal potential of an input signal consisting of a pedestal signal and a burst signal superimposed thereto to a specified potential.
BACKGROUND OF THE INVENTION
In general, average potential of video signals varies according to the information it contains, especially according to the brightness of the video signals. Therefore, a clamping circuit (described as a pedestal clamping circuit hereinafter) is generally provided in a semiconductor integrated circuit used for processing video signals, in order to keep a sink chip DC (DC indicates a direct current hereinafter) potential or a pedestal DC potential at a constant value.
This pedestal clamping circuit requires a clamping pulse synchronized to a timing of a pedestal signal to maintain a pedestal level at a constant DC potential. For a period when this clamping pulse is received in the pedestal clamping circuit, comparison is made between a pedestal DC potential of an input video signal and a DC potential of a clamping target (described as a reference potential hereinafter).
The difference obtained through the comparison is fed back, and the potential of the DC component of the video signal is adjusted according to the difference, by which the pedestal DC potential can be kept constant. Accordingly, when a timing of a clamping pulse is displaced from a timing of a pedestal signal, the pedestal signal can not be clamped to a desired DC potential.
FIG. 7
shows a simulated view of a pedestal clamping circuit based on the conventional technology. This pedestal clamping circuit comprises an input terminal
11
to which a video signal is inputted from an external device, a resistor
12
with one terminal thereof connected to the input terminal
11
, a comparator
13
with a reversed input terminal thereof connected to the other terminal of the resistor
12
, a constant voltage power unit
14
for loading a reference potential Vped to a non-reversed input terminal of the comparator
13
, a pair of variable current sources
15
,
16
connected to the other terminal the resistor
12
and an amount of current of each of which is controlled by output from the comparator
13
, and a feedback capacitor
17
connected to an output terminal of the comparator
13
.
A clamping pulse is inputted into the comparator
13
at a specified timing. Output from the pedestal clamping circuit can be obtained at the other edge of the resistor
12
. The variable current source
15
is connected between the other edge of the resistor
12
and a positive supply voltage Vcc, while the variable current source
16
is connected between the other edge of the resistor
12
and a ground GND.
Effects due to the pedestal clamping circuit shown in
FIG. 7
are explained. A video signal having been inputted from the input terminal
11
is then inputted to the reversed input terminal of the comparator
13
through the resistor
12
. The video signal inputted into the comparator
13
consists of a pedestal signal to which a burst signal is superimposed as a reference for a color density or a color tone. The comparator
13
compares a potential of a video signal to the reference potential Vped during a period when a clamping pulse is received (e.g., a period when a clamping pulse is a relatively high potential level (described as a “H (high)” level hereinafter)), generates and outputs a feedback signal S
1
according to the difference and outputs. The feedback signal S
1
is fed back to the variable current sources
15
,
16
.
As a result of the feedback, when a potential of the video signal is lower than the reference potential Vped, current flows into the resistor
12
from the variable current source
15
which is at a higher potential so that the potential of the video signal is higher. On the contrary, when the potential of the video signal is higher than the reference potential Vped, current is drawn out from the resistor
12
by the variable current source
16
which is at a lower potential so that the potential of the video signal becomes lower. Thus, the resistor
12
and the variable current source
15
form a positive potential loading unit, while the resistor
12
and the variable current source
16
form a negative potential loading unit.
The capacitor
17
is charged or discharged according to an output from the comparator
13
. This capacitor
17
maintains the charged state for a period when a clamping pulse is not received (e.g., a period when a clamping pulse is at a relatively low level (described as a “L (low)” level hereinafter)).
FIG. 8
shows a detail circuit configuration of the pedestal clamping circuit. This pedestal clamping circuit has an emitter-follower circuit
21
comprising an NPN transistor Tr
1
. A positive power voltage Vcc is applied to the collector of the NPN transistor Tr
1
of this emitter-follower circuit
21
, the emitter is branched and connected to one terminal of the resistor
12
and to the ground GND through another resistor
22
, and a video signal is inputted into the base thereof.
This pedestal clamping circuit has a differential amplifier. The differential amplifier comprises a constant current source
23
connected to a power line with a positive power voltage Vcc applied thereto, a differential pair
24
of PNP transistors Tr
2
, Tr
3
the emitters of each of which are connected to the constant current source
23
, and a current mirror circuit
25
comprising a pair of NPN transistors Tr
4
, Tr
5
connected to the differential pair
24
respectively. The differential pair
24
and current mirror circuit
25
correspond to the variable current source
15
and to the variable current source
16
shown in
FIG. 7
respectively.
A specified bias potential is applied to the base of the PNP transistor Tr
2
by a DC bias source
26
. Inputted to the base of the PNP transistor Tr
3
is an output from a circuit constituting a comparator described later. Collectors of the PNP transistors Tr
2
, Tr
3
are connected to the collectors of the NPN transistors Tr
4
, Tr
5
.
The base terminals of the pair of NPN transistors Tr
4
, Tr
5
are connected to the collector of the PNP transistor Tr
3
in the side where output (namely a feedback signal S
1
) from a circuit constituting the comparator described later is inputted to the base thereof in the differential pair
24
. Namely, in the NPN Transistor Tr
5
connected to the side where output from the comparator described later of the current mirror circuit
25
is inputted to the base thereof, the base and the collector thereof are short-circuited. Each emitters of the pair of NPN transistors Tr
4
, Tr
5
is connected to the ground GND.
The other terminal of the resistor
12
is connected to the output from the differential amplifier comprising the constant current source
23
, differential pair
24
and current mirror circuit
25
. In addition, the output from this differential amplifier is supplied to an external device, branched and inputted to a differential pair as one of circuits constituting the comparator described later.
The comparator comprises a current mirror circuit
27
comprising a pair of PNP transistors Tr
6
, Tr
7
each having an emitter connected to the power line with a positive voltage Vcc loaded thereto; a differential pair
28
of NPN transistors Tr
8
, Tr
9
connected to the current mirror circuit
27
; and a constant current source
29
to which emitters of the NPN transistors Tr
8
, Tr
9
constituting the differential pair
28
are connected through a switching element
30
.
This comparator corresponds to the comparator
13
shown in FIG.
17
. The output from this comparator is supplied to the base of the PNP transistor Tr
3
constituting the differential pair
24
of the differential amplifier as described above, branched and supplied to the feedback capacitor
17
. The other terminal of the constant current source
29
is connected to the ground GND.
The base terminals of the pair of PNP transistors Tr
6
, Tr
Hsia Sherrie
Matsubishi Denki Kabushiki Kaisha
McDermott & Will & Emery
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