Circuit for canceling thermal hysteresis in a current switch

Details Circuit for canceling thermal hysteresis in a current switch Circuit for canceling thermal hysteresis in a current switch

2002-01-31

2003-09-30

Jeanglaude, Jean Bruner (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S119000, C326S126000

Reexamination Certificate

active

06628220

ABSTRACT:

TECHNICAL FIELD OF THE DISCLOSURE
This invention relates to current switching techniques and more particularly to a circuit for canceling thermal hysteresis.
BACKGROUND OF THE DISCLOSURE
Current switches are utilized in various applications such as digital to analog converters (DACs) . In an application where time of switching is important, a current switch is commonly driven directly from a clocked latch or flip-flop, and
FIG. 1
is a schematic circuit diagram of a differential current switch
10
that is driven by the differential output OUT/OUTX of a high speed differential latch
20
. Without loss of generality, this may be considered to be one bit of a current-output DAC. The current switch
10
comprises two differentially connected transistors Q
9
, Q
10
which steer a current Idac into one or the other of complementary load terminals DACOUT, DACOUTX.
The differential latch
20
includes differentially connected transistors Q
1
, Q
2
that receive the respective phases of a differential logical input D/DX at their base terminals, and which have their emitter terminals connected together. The collector terminals of the differential pair of transistors Q
1
, Q
2
are respectively connected to the collector terminals of the differential pair of transistors Q
4
, Q
3
, and to the base terminals of emitter followers Q
7
, Q
8
. The emitter terminals of the emitter followers Q
7
, Q
8
are respectively connected to current sources I
2
, I
3
, and comprise differential outputs OUT/OUTX of the latch
20
. The emitter terminals of the emitter followers Q
7
, Q
8
are further respectively connected to the base terminals of the differential pair of transistors Q
3
, Q
4
. A resistor R
1
is connected between a supply voltage V+ and the node formed by the interconnection of the collector of the transistor Q
1
, the collector of the transistor Q
3
, and the base of the emitter follower Q
7
. A resistor R
2
is connected between the supply voltage V+ and the node formed by the interconnection of the collector of the transistor Q
2
, the collector of the transistor Q
4
, and the base of the emitter follower Q
8
.
The differential pair of connected transistors Q
5
, Q
6
receive the respective phases of a differential clock signal CLK/CLKX at their base terminals, and have their emitter terminals connected together to a current source I
1
. The collector terminal of the transistor Q
5
is connected to the emitter terminals of the differential transistors Q
1
, Q
2
, while the collector terminal of the transistor Q
6
is connected to the emitter terminals of the differential transistors Q
3
, Q
4
.
The power dissipation in the differentially connected switch transistors Q
9
, Q
10
will be approximately (neglecting the base current) Idac times the collector-emitter voltage of the transistor that is switched on, and essentially zero in the other transistor. The thermal response of a transistor can be approximated by a thermal resistance and a thermal time constant, such that temperature rise of each transistor at any time is a function of the past sequence of times that the transistor has been turned on.
The threshold voltage about which the current switch switches from one state to the other is nominally at zero volts differential between the bases of the transistors Q
9
, Q
10
. However, the transistors Q
9
, Q
10
are subject to differential heating due to the higher power dissipation in the transistor that is on and carrying the current. This in turn causes the threshold voltage for the switching to vary due to the temperature dependence of the base-emitter voltage. This effect is commonly referred to as “thermal hysteresis”.
The shift in threshold voltage due to the self heating can be modeled as the product of the temperature difference between the two transistors of the switch and the temperature coefficient of the base-emitter voltage. The output transition of the latch that drives the switch has a finite slew rate; if the threshold voltage of the switch varies, the effective time of the switch transition will vary by an amount equal to the threshold voltage change divided by the slew rate of the latch output. Such a variation in the time of switching, depending on the previous pattern of switch transitions, distorts the output of the DAC. The distortion products thus produced can limit the spur-free dynamic range of the DAC.
A known technique for reducing the variation in the time of switching due to differential self heating involves attempting to drive a current switch differential transistor pair with a sufficiently high slew rate drive signal that the time variation due to thermal threshold shift is very short, and/or keeping power density in the switching transistors low so that the differential heating is minimized. Low power density is achieved by using larger devices, which necessarily have higher parasitic capacitance. Higher slew rates for the drive signal result in more coupling to the output of the drive signal through any parasitic device capacitance that is present.
SUMMARY OF THE DISCLOSURE
The disclosed invention is directed to a current switch circuit including a first transistor and a second transistor as a differential transistor pair connected as a current switch and receiving a differential logic signal at their bases, and logic signal controlling circuitry coupled to the first and second transistors for offsetting a transition starting point of the differential logic signal to offset a self-heating induced shift in a switching threshold of the current switch.


REFERENCES:
patent: 4229729 (1980-10-01), Devendorf
patent: 4580066 (1986-04-01), Berndt
patent: 5781035 (1998-07-01), Tashibu
patent: 5790060 (1998-08-01), Tesch
Data Sheet (one page), Analog Devices, “High Speed Active Load With Inhibit Mode,” AD53041 1997.

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