Circuit for calibrating a resistance

Details Circuit for calibrating a resistance Circuit for calibrating a resistance

2005-09-20

2005-09-20

Deb, Anjan (Department: 2858)

Electricity: measuring and testing

Impedance, admittance or other quantities representative of...

Calibration

Reexamination Certificate

active

06946849

ABSTRACT:
A circuit for calibrating a resistance between a first circuit node and a second circuit node is disclosed. The circuit comprises a reference resistor connected between first and second reference nodes; a first transistor having a first current-handling terminal connected to the first reference node, a second current-handling terminal, and a first control terminal; and a second transistor having a third current-handling terminal connected to the first circuit node, a fourth current-handling terminal connected to the second circuit node, and a second control terminal connected to the first control terminal.

REFERENCES:
patent: 6448815 (2002-09-01), Talbot et al.
patent: 6549071 (2003-04-01), Paul et al.
patent: 2003/0090318 (2003-05-01), Ryoo et al.
Jafar Savoh and Behzad Razavi; “A 10Gb/S CMOS Clock and Data Recovery Circuit with Frequency Detection”; 2001 IEEE International Solid-State Circuits Conference; Digest of Technical Papers; First Edition; Feb. 5-7, 2001; pp. 78-79, 434.

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