Circuit for bipolar transistor stress and qualification

Details Circuit for bipolar transistor stress and qualification Circuit for bipolar transistor stress and qualification

2000-06-09

2002-08-20

Huynh, Kim (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S054000, C361S111000, C327S538000, C327S543000, C327S432000, C327S310000

Reexamination Certificate

active

06437956

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to the manufacture of bipolar transistors and, more specifically, to the testing of developmental bipolar transistors under controlled stress conditions to provide qualification for commercial use.
BACKGROUND OF THE INVENTION
Transistors are used as either amplifying or switching devices in electronic circuits. In the first application, the transistor functions to amplify small ac signals. In the second application, a small current is used to switch the transistor between an “on” state and an “off” state.
An “FET” is a field effect transistor. There are two major types of FET's, the metal-oxide-semiconductor field effect transistor or MOSFET (also called an insulated-gate FET, or IGFET), and the junction-gate FET, or JFET. An FET has a control gate, and source and drain regions formed in a substrate. The control gate is formed above a dielectric insulator that is deposited over the area between the source and drain regions. As voltage is applied to the control gate, mobile charged particles in the substrate form a conduction channel in the region between the source and drain regions. Once the channel forms, the transistor turns “on” and current may flow between the source and drain regions.
The bipolar transistor is an electronic device with two p-n junctions in close proximity. The bipolar transistor has three device regions: an emitter, a collector, and base disposed between the emitter and the collector. Ideally, the two p-n junctions (the emitter-base and collector-base junctions) are in a single layer of semiconductor material separated by a specific distance. Modulation of the current flow in one p-n junction by changing the bias of the nearby junction is called “bipolar-transistor action.”
External leads can be attached to each of the three regions and external voltages and currents can be applied to the device using these leads. If the emitter and collector are doped n-type and the base is doped p-type, the device is an “npn” transistor. Alternatively, if the opposite doping configuration is used, the device is a “pnp” transistor. Because the mobility of minority carriers (i.e., electrons) in the base region of npn transistors is higher than that of holes in the base of pnp transistors, higher-frequency operation and higher-speed performances can be obtained with npn devices. Therefore, npn transistors comprise the majority of bipolar transistors used to build integrated circuits.
In the manufacture of bipolar transistors, especially in the development of new bipolar transistor technology such as SiGe bipolar transistors, it is often necessary to put various populations of bipolar transistors under controlled stress conditions to qualify the transistors for commercial use. Presently, such transistors are stressed by exposing them to stress conditions that provide an approximation of constant current, constant voltage conditions for a predetermined time at a stress temperature. The stress conditions are determined for each application, but include parameters such as stress current, stress voltage, stress temperature, and stress duration. The stress temperature is typically provided by putting the transistor under stress in a stress oven.
A typical stress driver circuit
400
is shown in FIG.
1
. Stress conditions are applied by increasing the voltage
11
until the desired emitter current is reached. The transistor bias is provided by resistors
410
and
420
. The emitter current is determined by measuring the voltage drop across resistor
22
. A plurality of such circuits connected to a single voltage source for stressing a plurality of transistors are typically provided. Because the stress conditions depend on the characteristics of the transistor
18
under stress, the stress conditions will change as the characteristics of the transistor
18
change under stress. Also, each of the plurality of transistors will be under somewhat different stress conditions because each transistor typically has somewhat different characteristics.
Typically, after exposing the plurality of transistors to the predetermined stress conditions for a predetermined time, the stress conditions are removed, and the transistors are physically moved from the stress oven to a parametric tester for characterization. This characterization is done to measure any degradation of the transistor device parameters over the course of the stress testing. The transistors are then returned to the stress oven, and the procedure is repeated until the transistors have received the total predetermined amount of stress.
The standard testing method does not include “in situ” data collection while the transistors are under stress. There is some concern among those skilled in the art that characterizing a transistor after the stress conditions have been removed (and after the transistor has been physically handled) may provide some relaxation of the response of the transistor to stress. Therefore, the characterization performed after the stress has been interrupted may not portray a true picture of the response of the transistor to stress.
Furthermore, the standard stress driver circuit
400
does not provide for disconnection of the transistor upon failure. This shortcoming may cause the transistor to draw excessive current, which in turn may cause two problems. First, the excessive current draw from voltage source
11
in
FIG. 1
may affect the stress conditions of the other transistors in the plurality of test circuits, especially if a number of them begin to fail. Second, the failing transistor may draw enough current that it causes an excessive amount of physical damage to itself. This damage would render the part useless to post-stress physical failure analysis. The analysis of a transistor that has “burned out” does not provide useful information as to the mechanism of the failure. Accordingly, the standard method fails to provide a full understanding of the failure modes of the transistors that fail under stress.
Constant current source circuits, such as circuit
10
shown in
FIG. 2
, are well known in the art for providing a source of constant current I from a voltage source
11
to a load
12
. The circuit comprises an operational amplifier or “op amp”
14
, with voltage input or V
in
30
, a field effect transistor (FET)
16
, bipolar transistor
18
and a resistor
20
connected to an emitter node
24
, and a precision resistor
22
of resistance R. A node
25
is connected to the drain of FET
16
and to the collector of transistor
18
. Circuit
10
provides a constant current of I=V
in
/R to load
12
.
When the positive (+, or non-inverting) input of an op amp is higher (in voltage) than the negative (−, or inverting) input, the voltage at the output goes up. Conversely, when the negative input is higher than the positive input, the output goes down. It can be seen in
FIG. 2
that op amp
14
is connected in a negative feedback configuration. FET
16
and resistor
20
provide the base bias to transistor
18
. When the output of op amp
14
increases, the base bias increases, causing transistor
18
to conduct more, increasing its current flow, thereby increasing the emitter voltage (at resistor
22
). This increases the voltage at the negative input of op amp
14
, causing its output to decrease. This negative feedback configuration causes op amp
14
to maintain the voltage at the emitter of transistor
18
equal to V
in
. When in a negative feedback configuration, the output of an op amp will go to whatever voltage is necessary to maintain its inputs at equal voltages, as is well-known in the art.
Because the voltage at resistor
22
, having a resistance R, is maintained at V
in
, the current through resistor
22
is I=V
in
/R. For all practical purposes, there is negligible current flow into op amp
14
, and into the gate of FET
16
. Therefore, the current in resistor
22
is equal to the current in the load
12
. Because resistor
22
is of a precision resistance, and V
in
is set by an accurate voltage s

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