Circuit for biasing epitaxial regions with a bias voltage that i

Details Circuit for biasing epitaxial regions with a bias voltage that i Circuit for biasing epitaxial regions with a bias voltage that i

1996-02-27

1998-08-18

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

327535, 327545, H03K 301

Patent

active

057962928

ABSTRACT:
A circuit for biasing epitaxial wells of a semiconductor integrated circuit includes a first transistor and a second transistor driven in phase opposition to the first; when the supply voltage is positive, the first transistor, being connected between the power supply and the epitaxial well, is conducting whereas the second transistor is cut off. When, on the contrary, the supply voltage is negative, the second transistor, being connected between the epitaxial well and the ground reference GND, goes into saturation, thereby holding the epitaxial well biased to ground since, at that time, it is the highest potential present on the device. In this way, it becomes possible to always ensure reverse biasing of the parasitic diodes which form at the junctions between the epitaxial wells and the adjacent regions thereto.

REFERENCES:
patent: 5239207 (1993-08-01), Miyamoto et al.
patent: 5546020 (1996-08-01), Lee et al.
patent: 5631597 (1997-05-01), Akaogi et al.
patent: 5640123 (1997-06-01), Akaogi et al.

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