Amplifiers – With semiconductor amplifying device – Including particular biasing arrangement
Reexamination Certificate
2006-09-22
2009-02-03
Pascal, Robert (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including particular biasing arrangement
C330S290000
Reexamination Certificate
active
07486143
ABSTRACT:
An embodiment of a circuit for biasing a transistor such as an amplifier transistor includes reference and bias nodes, and includes buffer, reference, and feedback stages. The reference node receives a reference current, and the bias node, which is for coupling to the transistor, carries a bias signal. The buffer stage buffers the reference node from the bias node. The reference stage generates the bias signal from the reference current, and the bias signal causes the transistor to conduct a bias current that is proportional to the reference current. And the feedback stage is coupled between the reference and bias nodes. As compared to known bias circuits, such a bias circuit may reduce the amplitude and duration of a transient overshoot in the bias current of a field-effect transistor when the DC component of the transistor's drain voltage transitions from one value to another value. Such a bias circuit may also reduce the difference between the values of the bias current through the transistor for different supply voltages. And such a bias circuit may reduce the difference between the predicted and actual values of the bias current through the transistor for a given input voltage such as that between the gate and the source of a field-effect transistor.
REFERENCES:
patent: 6753734 (2004-06-01), Arell et al.
patent: 7057462 (2006-06-01), Kang et al.
patent: 7064614 (2006-06-01), Feng et al.
patent: 2007/0040613 (2007-02-01), Chow et al.
Rohdin Hans
Sun Wei John Shi
Avago Technologies Wireless IP (Singapore) Pte. Ltd.
Nguyen Hieu P
Pascal Robert
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