Circuit for biasing a bulk terminal of a MOS transistor

Details Circuit for biasing a bulk terminal of a MOS transistor Circuit for biasing a bulk terminal of a MOS transistor

2000-09-14

2002-09-24

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S535000

Reexamination Certificate

active

06456150

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a circuit for biasing a bulk terminal of a MOS transistor.
BACKGROUND OF THE INVENTION
As is known, in order to guarantee correct functioning of a MOS transistor in all operative conditions, it is necessary for the PN junctions present between the bulk region and the drain and source regions of the MOS transistor always to be biased inversely. In order to guarantee this inverse biasing, the bulk terminal of a PMOS transistor is always biased to the highest potential present in the circuit in which the PMOS transistor is inserted, whereas the bulk terminal of an NMOS transistor is biased to the lowest potential.
This condition must always be fulfilled, otherwise there is a risk that the said PN junctions will be biased directly, thus triggering so-called latch-up phenomena, i.e., the phenomena of conduction of parasitic components.
In some cases, however, the aforementioned condition is not simple to obtain, particularly when the potential to which the bulk terminal must be biased is not known a priori, but depends on the operating condition of the MOS transistor.
A typical example of this situation is obtained when the MOS transistor is used bi-directionally, i.e., when its source and drain terminals can change roles, depending on the direction of the current. In fact, in this case, if it is not possible to bias the bulk terminal to a potential which is always higher than the potentials of the drain and source terminals, there is a risk of direct biasing of the PN junctions, with the aforementioned consequences.
FIG. 1
illustrates by way of example a circuit in which there can be seen the undesirable situation of direct biasing of the PN junctions present between the bulk region and the drain and source regions of a PMOS transistor.
In particular,
FIG. 1
shows a first PMOS transistor
1
having a first terminal
1
a
connected to a first line
2
set to a first potential V
1
, a second terminal
1
b
, a bulk terminal
1
c
connected to a second line
4
set to a second potential V
2
, and a gate terminal
1
d
receiving a first control signal SC, with high and low logic levels defined respectively by the second potential V
2
and the ground potential, and which control respectively switching on and switching off of the PMOS transistor
1
.
In the example considered in
FIG. 1
, the second line
4
is connected to the output of a charge pump (not shown) which, when it is on, provides a potential VHV which is greater than the first potential V
1
, and is controlled by the first control signal SC in phase opposition with respect to the PMOS transistor
1
. In particular, when the PMOS transistor
1
is on, and connects to one another the first and the second line
2
,
4
, the charge pump is off, and thus the second potential V
2
is substantially equivalent to the first potential V
1
(minus the voltage drop across the PMOS transistor
1
). Whereas when the PMOS transistor
1
is off, the charge pump is on, and thus the second potential V
2
is greater than the first potential V
1
. In addition, in some applications, when the PMOS transistor
1
is off, the charge pump could also be off, and the second line
4
could be biased to a potential which is different from those described.
In the circuit in
FIG. 1
, direct biasing of the PN junctions present between the bulk region and the drain and source regions of the first PMOS transistor
1
can occur if the second potential V
2
drops below the first potential V
1
, as a result of an overload or specific operating requirements, by a quantity which is greater than the threshold voltage of a PN junction. In fact, in this case, the bulk terminal
1
c
of the first PMOS transistor
1
would be biased to a potential lower than the potential of the first terminal
1
a
of the PMOS transistor
1
itself, by a quantity which is greater than the threshold voltage of a PN junction, and thus the PN junction defined by the regions connected to the bulk terminal
1
c
, and to the first terminal
1
a
, would be biased directly, with the aforementioned consequences.
A known circuit solution, which in the above-described example makes it possible always to guarantee the inverse biasing of the PN junctions in any operating condition, is illustrated in FIG.
2
.
According to this solution, between the first PMOS transistor
1
and the first line
2
, there is interposed a second PMOS transistor
6
, which is provided in a different tub from that in which the first PMOS transistor
1
is provided, and has a first terminal
6
a
connected to the first line
2
, a second terminal
6
b
connected to the first terminal
1
a
of the first PMOS transistor
1
, a bulk terminal
6
c
connected to the second line
4
, and a gate terminal
6
d
receiving a second control signal SB, which has high and low logic levels defined respectively by the first potential V
1
and by the ground potential, and which control respectively switching on and switching off of the PMOS transistor
6
.
In the circuit in
FIG. 2
, direct biasing cannot occur of the PN junctions which are present between the bulk region and the drain and source regions of the first and second PMOS transistor
1
,
6
, since, when the PMOS transistors
1
,
6
are off, their bulk terminals
1
c
,
6
c
are biased respectively to the first and second potential V
1
, V
2
, and are therefore never biased to potentials which are lower than the potentials to which the other two terminals, respectively
1
a
,
1
b
and
6
a
,
6
b
, are biased.
However, the above-described circuit solution has the disadvantage that the two PMOS transistors
1
,
6
have rather large dimensions, and consequently the silicon area which they occupy, derived from implementation of this solution, is rather large.
SUMMARY OF THE INVENTION
The disclosed embodiments of the present invention provide a circuit for biasing the bulk terminal of a transistor, free from the disadvantages of the above-described solutions.
According to the disclosed embodiments of the present invention, a circuit is provided for biasing a bulk terminal of a MOS transistor, the transistor having a first terminal connected to a first line set to a first potential and a second terminal connected to a second line set to a second potential. The biasing circuit in accordance with one embodiment of the invention includes a second and a third MOS transistor having first terminals connected respectively to the first line and to the second line, second terminals connected to the bulk terminal of the MOS transistor, and control terminals connected respectively to the second and to the first line.
In accordance with another aspect of the present invention, the second and third MOS transistors have bulk terminals connected to the bulk terminal of the first MOS transistor.
In accordance with yet another embodiment of the present invention, the biasing circuit further includes a fourth MOS transistor having a first terminal connected to one from among the first and second notes, a second terminal coupled to the bulk terminal of the first MOS transistor, and a control terminal receiving a first control signal. Ideally the MOS transistor has a bulk terminal connected to the bulk terminal of the first MOS transistor.
In accordance with still yet another aspect of the present invention, the circuit further includes a fifth MOS transistor having a first terminal coupled to one from among the second node and a ground node, a second terminal connected to the bulk terminal of the first MOS transistor, and a control terminal receiving a second control signal. Ideally the fifth MOS transistor has a bulk terminal connected to the bulk terminal of the MOS transistor.


REFERENCES:
patent: 5444397 (1995-08-01), Wong et al.
patent: 5719525 (1998-02-01), Khoury
patent: 5990705 (1999-11-01), Lim
patent: 6208178 (2001-03-01), Chen

Affiliated with

Also associated with

Rating

Circuit for biasing a bulk terminal of a MOS transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit for biasing a bulk terminal of a MOS transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit for biasing a bulk terminal of a MOS transistor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2906187