Circuit for auto-centering control loop bias currents

Details Circuit for auto-centering control loop bias currents Circuit for auto-centering control loop bias currents

1999-09-30

2001-01-30

Kim, Jung Ho (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C327S087000, C327S361000

Reexamination Certificate

active

06181187

ABSTRACT:

FIELD OF THE INVENTION
This invention generally relates to control loop bias currents. More particularly, it relates to a circuit for auto-centering a control loop bias current using a high impedance CMOS current driver.
BACKGROUND OF THE INVENTION
Many important system level circuit functions, such as automatic gain control (AGC) and phase-locked loops (PLL), use the general control loop as shown in FIG.
1
. The function block
10
would consist of a variable gain amplifier (VGA) in the case of a AGC loop, or a voltage controlled oscillator (VCO) in the case of a PLL system. The bias
12
to the function block
10
is controlled by a feedback loop (V
sense
)
14
which senses the current state of the function block, and compares it to the desired state (V
ref
)
16
resulting in an adjustment of the bias I
Bias
12
by I
Error
18
provided by the Gm block
20
. The digital-to-analog converter (DAC)
22
generates the main bias current (I
Center
)
24
to the function block
10
, and is adjustable through an external register. This programmable DAC extends the operational range of the function block, as well as, limits the gain and range of the Gm block needed for proper control loop functionality.
In the circuit described above, it is desirable to keep the Gm block operating at or near its zero differential operating point in order to maintain its optimal linearity and noise rejection characteristics. The farther the center current is from the desired bias current, the greater error current the Gm block must provide, and therefore must deviate from it's optimal operational point. If the DAC block could adjust or “adapt” the centering current, for which it provides, to the changing bias current needs of the function block, then the Gm block would need only provide the transitory error current for the loop during the acquisition period, and would always operate at it's zero differential point during steady state.
SUMMARY OF THE INVENTION
The present invention provides a method and circuit for automatically centering the control loop bias current by sensing and “memorizing” the total steady state bias current used by the function block (VGA or VCO) through the use of both digital and analog memory elements.
The present invention uses an auto-zeroing, high-impedance current driver to supply the bias current. This current driver cancels out offset currents by exploiting the high output impedance nature of CMOS current drivers as described in the cofiled application cited above. The invention uses cascoded or resistor source degenerated FET devices to create two very high impedance current sources. The mismatch between the bias currents is balanced to reduce the offset current using an auto-zeroing circuit.
An advantage of the present invention is the non-intrusive nature of the digital centering. Prior art circuits typically would cause transitions on the bias current input to the function block upon completion of updating the digital portion of the centering current. Advantageously, in the present invention the bias current is held constant while updating the digital portion of the bias current. Thus, when the bias current loop is closed and the bias current is again allowed to adjust with the feedback from the function block there is no transition on the bias current. This is particularly advantageous where the function block continues to operate during the auto-centering process.
Another advantage of the present invention is its versatility. The auto-centering control loop bias current can be used for common control loops such as phase locked loops and automatic gain control circuits.


REFERENCES:
patent: 4456840 (1984-06-01), Ide et al.
patent: 5892376 (1999-04-01), Tabatabai et al.
patent: 6072339 (2000-06-01), Bertolini

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