Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1998-11-03
2002-07-23
Shankar, Vijay (Department: 2778)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
Reexamination Certificate
active
06424325
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a circuit for driving a flat panel display in a sub field mode. Information to be displayed is provided as a succession of frames, each to be displayed during a corresponding field period. Such a display includes a plurality of display elements arranged in a matrix of rows and columns, and a plurality of first electrodes, each first electrode of the plurality of first electrodes being associated with display elements in a respective row or column. A circuit of this type includes a timing generator which divides a field period of a received display information into consecutive sub field periods, each sub field period including an address period preceding a display period, and each sub field period having a respective weight factor associated therewith. A drive circuit supplies drive signals, during the sub field periods corresponding to the respective weight factors, to respective addressed electrodes of the plurality of first electrodes. Each display element which is to be lit during a field period is addressed in one or more of the sub field periods, the sum of the weight factors associated with those sub field periods determining the luminance with which the display element is lit.
The invention also relates to a flat panel display apparatus having such a flat panel display and such a circuit for driving the flat panel display, and to a method of driving a flat panel display.
2. Description of Related Art
U.S. Pat. No. 5,541,618 discloses a method and a circuit for gradationally driving a flat panel device such as a Plasma Display Panel (further referred to as PDP). A PDP comprises a plurality of cells formed at cross points of scan electrodes and data electrodes which are arranged orthogonal to the scan electrodes. A picture to be displayed has a frame rate of 60 Hz. Each frame of the picture to be displayed is associated with a field period which is divided into a plurality of sub field periods. Each such field period comprises an address period and a display period. In each address period, the cells to be lit during the subsequent display period are addressed by sequentially selecting the scan electrodes and supplying appropriate data to the data electrodes for each selected scan electrode. In this way a desired charge is stored in the cells to be lit. During each display period sustain pulses are supplied to all the cells to light the cells in which the desired charge is stored. The brightness of a lit cell is determined by the number or the frequency of the sustain pulses. In a preferred embodiment, each display period has a different number of sustain pulses, and the frequency of the sustain pulses is equal for every display period. The number of sustain pulses of the display periods essentially have a ratio of 1:2:4:8: . . . 128. Therefore, the durations of the display periods have also this ratio. The cells or picture elements for the picture to be displayed are each represented by a binary coded data word in which each bit corresponds to one of the sub frames such that the length of the display period of that sub field is in accordance with the weight of the data bit in the data word. The cell is lit during the display period of a certain sub field of the bit of the data word associated with this certain sub field indicates such. So, the bits of the data word determine during which sub frames of a frame the cell produces light. The visual brightness of each cell is determined by the number of sustain pulses accumulated during the entire frame period.
It is a drawback of the method and the circuit for gradationally driving a PDP according to U.S. Pat. No. 5,541,618 that a large area flicker occurs in certain conditions. The large area flicker occurs most noticeably if large areas of cells are lit only during the sub field with the longest display period. A large contribution to the luminance output is generated during a very limited period in time during a frame. These light pulses occur with the repetition frequency of the frame. At a frame repetition frequency of 60 Hz, the eye might integrate the separate light pulses such that a flicker is not very annoying. But, at a frame repetition frequency of 50 Hz the gap in time between the light pulses is so large that the eye clearly detects an annoying flicker. A same reasoning holds if a large area of cells is lit during a sub field with a display period which is not the longest. However, the flicker will be somewhat less as the amount of flicker detected by the eye also depends on the amount of light generated.
BRIEF SUMMARY OF THE INVENTION
It is an object of the invention to provide a drive for a flat panel display such that less flicker occurs.
To this end, a first aspect of the invention provides a circuit for driving a flat panel display having a plurality of first electrodes partitioned into two groups. The first group are driven by signal corresponding to sub field periods in which each of the sub field periods has a weight factor associated with it, and the weight factors for the corresponding sub field periods occur in a predetermined order. The second group is similarly driven by signals corresponding to sub field periods each having a respective weight factor, but the weight factors occur in a different predetermined order. A second aspect of the invention provides a flat panel display apparatus with a flat panel display and a circuit for driving the flat panel display as just described. A third aspect of the invention provides a method of driving such a flat panel display. Advantageous embodiments of the invention are defined in the dependent claims.
An AC plasma display is a bilevel display with a memory function, i.e. it can only turn pixels on or off. To switch a pixel on, a prime sequence (addressing period) is necessary. In such a sequence a pixel that should turn on is conditioned, in such a way, that it turns on when a voltage is put across the scan and sustain electrodes (during the display period). This is done for all pixels in a display that should turn on. The grayscale itself is now generated in such a way that the luminance value is divided into several subfields with various weights. When for a subfield in a display all pixels that should be turned on are primed, the scan and sustain voltage is put on the display for the sustain period corresponding to the weight of that subfield and all primed pixels turn on. In the next subfield this process is repeated for that subfield with the corresponding subfield weight. The weight of a subfield determines how long the pixels are turned on. The luminance value of a pixel is determined by the input byte of Red. Green or Blue (RGB). When the weight of the subfields correspond to the weight of the input bits of a pixel, the weight of a bit corresponding to the subfield weight determines whether this pixel is primed, i.e. whether this pixel is turned on during the sustain period.
When large areas are lit using only one subfield with a high bit weight, in only one moment in time a large contribution to the luminance output is generated. This results in large area flicker with large frequency components of 50 or 60 Hz for which the eye is quite sensitive. The method to be proposed reduces large area flicker behavior when planes of one grayscale are shown, especially when only a few subfields (MSB) generate the luminance in a filed. To overcome the large area flicker in these cases, the odd and even rows are addressed in different groups, and the subfield order of the odd and even rows are chosen differently from each other, so that the odd and even rows are in anti-phase with respect of each other for the subfields with the highest bit weights. This reduces the large area flicker considerable for the frequency components of 50 and 60 Hz. The eye observes both rows at the same time and will mainly see frequency components around 100 or 120 Hz for which the eye is less sensitive.
The above described sub field order is a preferred embodiment of the invention. It is also possible t
Frenel Vanel
Shankar Vijay
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