Boots – shoes – and leggings
Patent
1989-02-14
1991-06-25
Shaw, Dale M.
Boots, shoes, and leggings
364745, 36471504, G06F 738, G06F 700
Patent
active
050273086
ABSTRACT:
In a floating-point addition (and/or subtraction) of two normalized numbers where a normalized result is also desired, a generation of a carry (overflow) or a borrow from the most significant bit of a minuend operation will cause the resultant mantissa not to be normalized. A dual adder scheme is used to always provide a normalized result. One adder provides an unshifted result while the second adder provides a shifted result. A logic circuit looks for a carry out when performing addition and a bit value of the msb when performing subtraction to select the output from the adder providing the proper normalization. Rounding logic circuitry is used to predict the rounding of the resultant mantissa and carry bits are coupled as a carry-in to the adders to achieve the proper rounding in the same clock cycle as the adding/subtracting of the two mantissas.
REFERENCES:
patent: 4308589 (1981-12-01), Joyce et al.
patent: 4338675 (1982-07-01), Palmer et al.
patent: 4484259 (1984-11-01), Palmer et al.
patent: 4562553 (1985-12-01), Mattedi et al.
patent: 4639887 (1987-01-01), Farmwald
patent: 4758972 (1988-07-01), Frazier
patent: 4922446 (1990-05-01), Zurawski et al.
ANSI/IEEE, IEEE Standard for Binary Floating-Point Arithmetic, Aug. 12, 1986.
Chan Alfred K.
Galbi David
Sit Hon P.
Intel Corporation
Shaw Dale M.
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