Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data
Reexamination Certificate
1998-10-20
2001-05-08
Ghebretinsae, Temesghen (Department: 2631)
Pulse or digital communications
Synchronizers
Synchronizing the sampling time of digital data
C341S131000
Reexamination Certificate
active
06229860
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit for accurately converting digitized analog signals into digital signals, and more particularly to a circuit for converting digitized analog video signals into digital video signals served to a liquid crystal display (hereinafter referred as LCD) panel.
2. Description of the Prior Art
Owing to the increasing functions of a personal computer, analog signals such as video signals or audio signals can be processed and modified by the multimedia unit of a computer, the processed digital signals must be reverted to analog signals by a D/A converter such that the signals can be received by a common speaker or a conventional CRT monitor. Such reverted analog signals are different from original analog signals, which as shown in FIG.
1
(
a
), are referred as “digitized analog signals”, as shown in FIG.
1
.
If the digitized analog signals must be sampled again by some digital devices (devices that receive digital signals only, e.g. LCD panels) to be converted to digital signals, some conditions must be satisfied for the digitized analog signals to be accurately reverted to the original digital signals. Next, the video signals and the conditions that are applied to an LCD panel are used to exemplify the sampling process.
An LCD panel is a device which can only receive digital signals. However, video signals output from a display card of a common personal computer are digitized analog signals as stated in the above. When such video signals enter an LCD panel, an A/D converter must be used to perform sampling such that digital signals are obtained. If the sampling cannot be performed accurately or the sampling is performed ambiguously, the displayed picture will become distorted or unclear.
Referring to
FIG. 2
, in which the sampling clock CLK (triggering at rising edges) is not a proper sampling signal, for not only does it cause the digital signal to become distorted (comparing the digital signal b
0
b
1
b
2
b
3
b
4
b
5
shown in the lower
FIG. 2
with the digitized analog signal shown in the upper FIG.
2
), but also produce some imprecise signals.
FIG. 3
shows three different kinds of sampling clocks CLK
1
, CLK
2
and CLK
3
, in which only CLK
3
is an ideal sampling clock. This is illustrated in the following: the actuating points of CLK
1
are not ideal, because ambiguous results are produced repetitively. Accordingly, the ambiguous results that are produced repetitively can be prevented only when the frequency of the sampling clock is the same as that of the original digital signal of the digitized analog signal. Although CLK
2
satisfies the above conditions, but the actuating points of most digital electrical elements have limitations on setup time and hold time, and the requirements on setup time and hold time are different for different elements. In
FIG. 3
, the sampling points of CLK
2
are at the changing edges of the signal. Thus, for an A/D converter, the sampled data may be signals that are before or after the change. Therefore the actuating points of the sampling are not ideal.
CLK
3
is an ideal sampling clock, because a precise signal can be sampled by each of the actuating points of the sampling, and no signal is omitted. Thus it is a good sampling clock.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a circuit for auto-searching a precise sampling clock for an A/D converter, and to prevent the signal from becoming distorted or ambiguous in the converting process.
Referring to
FIG. 4
, the circuit according to the present invention for accurately converting digitized analog signals into digital signals comprises: a clock signal synthesizer
1
, an A/D converter
2
, an A/D converter
3
, a digital subtractor
4
, a CPU
5
, a phase modulator
6
, and an A/D converter
7
.
A clock signal synthesizer
1
accepts a synchronizing signal and a frequency-indicating signal, and outputs a clock signal CLK
1
in accordance with the synchronizing signal and the frequency-indicating signal.
An A/D converter
2
accepts a digitized analog signal and the clock signal CLK
1
output from the clock signal synthesizer
1
, and converts the digitized analog signal into a first digital signal in accordance with sampling points of the clock signal CLK
1
;
An A/D converter
3
accepts the digitized analog signal and a clock signal CLK
2
that is output from the clock signal synthesizer and then delayed by two buffers, and converts the digitized analog signal into a second digital signal in accordance with the sampling points of the delayed clock signal;
A digital subtractor
4
accepts the first digital signal and the second digital signal, and outputs their subtracted result.
A CPU
5
accepts an ERR signal output from the digital subtractor
4
, outputs a frequency-indicating signal to the clock signal synthesizer in accordance with the ERR signal, and outputs a phase-indicating signal.
A phase modulator
6
accepts a horizontal synchronizing signal H-Sync and the phase-indicating signal output from the CPU
5
, modulates the phase of said horizontal synchronizing signal H-Sync in accordance with the phase-indicating signal, and transfers the phase-modulated horizontal synchronizing signal to the clock signal synthesizer as its synchronizing signal; and
An A/D converter
7
accepts the digitized analog signal and a clock signal output from the clock signal synthesizer and then delayed by one buffer, and outputs a digital signal that is the output signal of the whole circuit.
Referring to
FIG. 7
, the circuit in
FIG. 4
acts as the following:
(1) If the ERR signal output from the digital subtractor is in a low level, the digital signal output from the third A/D converter is desired; proceed to step (2) otherwise;
(2) The CPU emits a phase-indicating signal to the phase modulator for delaying the phase of the horizontal synchronizing signal H-Sync, and further delaying the phase of the clock signal CLK
1
output from the clock signal synthesizer, then proceed to step (3);
(3) Check if the phase delay of the clock signal CLK
1
has exceeded one period; if not, proceed to step (1); proceed to step (4) otherwise;
(4) The CPU emits the phase-indicating signal to clock signal synthesizer for changing the frequency of output clock signal CLK
1
, then return to step (1).
In addition, the circuit according to the present invention for accurately converting digitized analog signals into digital signals further comprises a pre-amplifier
8
for pre-amplifying the digitized analog signal, which then enters the third A/D converter
7
.
REFERENCES:
patent: 5831488 (1998-11-01), Nakajima et al.
Amtran Technology Co. Ltd.
Bacon & Thomas PLLC
Ghebretinsae Temesghen
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