Circuit for accurate memory read operations

Details Circuit for accurate memory read operations Circuit for accurate memory read operations

2002-12-05

2004-05-04

Mai, Son (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185030, C365S185250

Reexamination Certificate

active

06731542

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to the field of semiconductor devices. More particularly, the present invention relates to semiconductor memory devices.
BACKGROUND ART
Memory devices are known in the art for storing data in a wide variety of electronic devices and applications. Electronic memory, for example, is widely used in a variety of commercial and consumer electronic products. A typical memory device comprises a plurality of memory cells. Often, memory cells are arranged in an array format, where a row of memory cells corresponds to a word line and a column of memory cells corresponds to a bit line, and where each memory cell defines a binary bit, i.e., either a zero (“0”) bit or a one (“1”) bit. For example, a memory cell may be defined as either being a “programmed” cell or an “erased” cell. According to one particular convention, a programmed cell is representative of a “0” bit, and an erased cell is representative of a “1” bit. In one type of memory cell, each cell stores two binary bits, a “left bit” and a “right bit.” The left bit can represent a “0” or a “1” while the right bit can represent a “0” or a “1” independent of the left bit.
Typically, the state of a memory cell is determined during a read operation by sensing the current drawn by the memory cell. For example, to ascertain the current drawn by a particular memory cell, the drain terminal of the memory cell is connected to a sensing circuit, the source terminal of the memory cell is connected to ground, and the gate of the memory cell is selected. The sensing circuit attempts to detect the current drawn by the memory cell, and compares the sensed memory cell current against a reference current. If the sensed memory cell current exceeds the reference current, the memory cell is considered an erased cell (corresponding to a “1” bit). However, if the sensed memory cell current is below the reference current, the memory cell is considered a programmed cell (corresponding to a “0” bit).
In practice, it is desirable to have the sensed memory cell current be greater than or less than the reference current by an error margin. With an error margin, the impact of extraneous factors, such as noise, for example, upon the detection of the memory cell current is reduced. For instance, suppose the reference current used for comparison is fifteen (15) microAmps (&mgr;A) in a particular memory device. In this case, it would be desirable to sense a memory cell current of twenty (20) &mgr;A or greater for an erased cell (corresponding to a “1” bit) and a memory cell current of ten (10) &mgr;A or less for a programmed cell (corresponding to a “0” bit). With a five (5) &mgr;A error margin, the impact of factors, such as noise, is significantly reduced.
Conventional memory read circuits, however, considerably reduce the error margin for sensing memory cell current during read operations. When the error margin is significantly reduced, the reliability of sensing the memory cell current also decreases, since factors, such as noise, have a greater impact. The reliability of the read operation is thus reduced resulting in poor performance of the memory device. Accordingly, there exists a strong need in the art to overcome deficiencies of known memory read circuits and to provide a memory read circuit and technique which results in increased error margins in a fast and accurate manner during memory read operations.
SUMMARY
The present invention is directed to circuit for accurate memory read operations. The invention addresses and resolves the need in the art for a memory circuit arrangement which results in increased error margins in a fast and accurate manner during memory read operations. According to one exemplary embodiment, the memory circuit arrangement for sensing current in a target cell during a read operation comprises the target cell and a first neighboring cell adjacent to the target cell. In the exemplary embodiment, the target cell has a first bit line connected to ground; the target cell also has a second bit line connected to a sensing circuit. The first neighboring cell shares the second bit line with the target cell, and further has a third bit line connected to the sensing circuit. Each of the target cell and the first neighboring cell comprises a respective gate terminal connected to a common word line. In some embodiments, the target cell may also store a first bit and a second bit.
According to another exemplary embodiment, the memory circuit arrangement further comprises a second neighboring cell adjacent to the first neighboring cell. In this particular embodiment, the second neighboring cell shares the third bit line with the first neighboring cell, and further has a fourth bit line connected to a precharge circuit during the read operation. Each of the target cell, the first neighboring cell, and the second neighboring cell comprises a respective gate terminal connected to a common word line.
According to another exemplary embodiment, the memory circuit arrangement further comprises a third neighboring cell adjacent to the second neighboring cell. In this particular embodiment, the third neighboring cell shares the fourth bit line with the second neighboring cell, and further has a fifth bit line connected to the precharge circuit during the read operation. Each of the target cell, the first neighboring cell, the second neighboring cell, and the third neighboring cell comprises a respective gate terminal connected to a common word line.
Other features and advantages of the present invention will become more readily apparent to those of ordinary skill in the art after reviewing the following detailed description and accompanying drawings.


REFERENCES:
patent: 5400276 (1995-03-01), Takeguchi
patent: 6496405 (2002-12-01), Hibino
patent: 6510082 (2003-01-01), Le et al.
patent: 6529412 (2003-03-01), Chen et al.
patent: 6532176 (2003-03-01), Kushnarenko
Tsao et al., “A 5V-Only 16M Flash Memory Using a Contactless Array of Source-Side Injection Cells,” 1995 Symposium on VLSI Circuits, IEEE, New York, Jun. 8, 1995, p. 77-78.

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