Pulse or digital communications – Transceivers
Reexamination Certificate
1999-11-23
2004-09-21
Ghebretinsae, Temesghen (Department: 2631)
Pulse or digital communications
Transceivers
C307S043000, C307S401000, C307S071000, C326S062000, C326S082000, C326S030000, C327S108000
Reexamination Certificate
active
06795493
ABSTRACT:
BACKGROUND OF THE INVENTION
A. Field of the Invention
The present invention relates to a circuit for a transceiver output port of a local area networking device, especially to a circuit for a transceiver output port which is operable at low supply voltage and can output a differential signal for an Ethernet networking device.
B. Description of the Prior Art
The IEEE develops a twisted-pair standard for 10 Mbps Ethernet called 10 BASE-T. 10 BASE-T Ethernet has a star wiring configuration and a UTP cable which connects each workstation to a central hub. According to the IEEE 802.3 Ethernet standard, the peak voltage for a transceiver output port ranges from ±2.2V to ±2.8V. In other words, the differential signal V
PP
of the transceiver output port ranges from 4.4V to 5.6V as illustrated in FIG.
1
. The differential signal of the transceiver output port
21
is transmitted to a twisted-pair cable
22
via the transformer
23
, as illustrated in FIG.
2
.
Referring to
FIG. 3
, which shows a conventional circuit of a transceiver output port for communicating with the UTP cable. It includes two current sources: I
1
and I
2
which are series-connected to the resistors R
1
and R
2
respectively. The other ends of the resistors R
1
and R
2
are connected to a common supply voltage V
DD
. A differential voltage (V
+
−V
−
) appears between the nodes x and y, which have voltages V
+
and V
−
respectively. An equivalent load resistance R
L
appears between the nodes x and y.
The advantage for the circuit as illustrated in
FIG. 3
is that electricity can be saved while the circuit is in idle state. When there is no signal output from the transceiver output port (the transceiver output port is idle), the current sources I
1
, I
2
can be completely opened in order to save electricity. However, due to the inductance of the transformer coil, it takes a period of time for the transformer coil to be fully charged every time after the current sources I
1
, I
2
are closed. The time required is determined by the inductance value of the transformer coil and the resistors R
1
, R
2
. Consequently, for the purpose of suppressing the time delay as mentioned in the above, the current sources I
1
, I
2
cannot be completely opened even in idle state in practical application.
Although the circuit as shown in
FIG. 3
can save electricity, it is not applicable under low supply voltage, which is explained as follows. Referring to
FIG. 3
, assume R
L
is the equivalent load resistance of the UTP cable, and R
1
and R
2
are the bias resistors for matching impedance. Generally, the following expression holds: R
L
=2R
1
=2R
2
=100&OHgr;. Therefore, the resistors R
1
and R
2
can both be represented as R; R
L
can be represented as
2
R, respectively. Accordingly, the following equations can be derived:
I
1
+
I
2
=
I
(
1
)
V
DD
-
V
-
R
+
V
+
-
V
-
2
R
=
I
1
(
2
)
V
DD
-
V
+
R
-
V
+
-
V
-
2
R
=
I
2
(
3
)
wherein I is a constant.
From the equations (2) and (3), equation (4) can be derived as follows:
⇒
2
V
DD
-
(
V
+
+
V
-
)
R
=
I
⇒
V
+
+
V
-
=
2
V
DD
-
RI
⇒
V
-
=
2
V
DD
-
R1
-
V
+
(
4
)
Substitute equation (2) into equation (4) to obtain equation (5) as follows.
⇒
2
V
DD
-
2
(
2
V
DD
-
RI
-
V
+
)
+
V
+
-
(
2
V
DD
-
RI
-
V
+
)
2
R
=
I
1
⇒
-
4
V
DD
+
4
V
+
+
3
RI
=
2
RI
1
(
5
)
Substitute equation (1) into equation (5) to obtain equation (6) as follows.
⇒
V
+
=
V
DD
-
1
4
RI
1
-
3
4
RI
2
(
6
)
Furthermore, substitute equation (4) into equation (6) to obtain equation (7) as lows.
⇒
V
-
=
V
DD
-
3
4
RI
1
-
1
4
RI
2
(
7
)
From equations (6) and (7),
⇒
V
+
-
V
-
=
R
2
(
I
1
-
I
2
)
(
8
)
When the differential signal is positive (V
+
>V
−
), we can derive an equation (9) from the equation (8).
2.2
≤
V
+
-
V
-
=
R
2
(
I
1
-
I
2
)
≤
2.8
⇒
4.4
R
+
I
2
≤
I
1
≤
5.6
R
+
I
2
(
9
)
From equation (7),
V
-
=
V
DD
-
3
4
RI
1
-
1
4
RI
2
≥
0
⇒
V
DD
≥
R
4
(
3
I
1
+
I
2
)
(
10
)
Substitute equation (9) into equation (10).
V
DD
≥
R
4
(
3
×
4.4
R
+
3
I
2
+
I
2
)
=
3.3
+
RI
2
As a result, the supply voltage VDO has a minimum value of 3.3V when I
2
=0. Therefore, the supply voltage V
DD
cannot be further reduced if the same amplitude of output signal is to be kept. This is a disadvantage for designing a circuit operable at low supply voltage.
SUMMARY OF THE INVENTION
To solve the above-mentioned problem, the present invention provides a circuit for a transceiver output port of a local networking device which is operable at low supply voltage and can output a differential signal for an Ethernet networking device. The circuit of the present invention includes four current sources. The first current source has a first terminal connected to ground and a second terminal connected to one terminal of a first resistor. The other terminal of the first resistor is connected to a supply voltage. A second current source has a first terminal connected to ground and a second terminal connected to one terminal of a second resistor. The other terminal of the second resistor is connected to the supply voltage. The resistance values of the first resistor and the second resistor are both equal to ½ that of the UTP cable for the purpose of impedance matching. In addition, a third current source and a fourth current source connect to the first resistor and the second resistor in parallel. In other words, the third current source is coupled between the first current source and the supply voltage while the fourth current source is coupled between the second current source and the supply voltage. As a result, the third current source and the fourth current source provide additional current which sustains a predetermined amplitude of differential signals output from the circuit. In this way, the supply voltage can be reduced as much as possible to a minimum value required to ensure proper operation of the four current sources.
REFERENCES:
patent: 5081423 (1992-01-01), Koyama et al.
patent: 5436934 (1995-07-01), Co
patent: 5818269 (1998-10-01), Brown et al.
patent: 6121793 (2000-09-01), Pickering et al.
patent: 6215816 (2001-04-01), Gillespie et al.
patent: 6313670 (2001-11-01), Song et al.
patent: 6393062 (2002-05-01), Furman et al.
patent: 6411647 (2002-06-01), Chan
Ghebretinsae Temesghen
Kumar Pankaj
Realtek Semiconductor Corp.
Thomas Kayden Horstemeyer & Risley
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