Circuit for a low power mode

Details Circuit for a low power mode Circuit for a low power mode

2009-02-18

2010-11-02

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S544000

Reexamination Certificate

active

07825720

ABSTRACT:
A circuit has a first transistor having a first current electrode coupled to a first supply voltage terminal and a second current electrode coupled to a virtual supply voltage node. A second transistor has a first current electrode coupled to the first supply voltage terminal and a control electrode coupled to the virtual supply voltage node. A first load has an input and has an output coupled to a second current electrode of the second transistor. A third transistor has a control electrode coupled to the output of the first load. A second load has an input coupled to the first supply voltage terminal, and has an output that is coupled to both a control electrode of the first transistor and a first current electrode of the third transistor. The virtual supply voltage node provides an operating voltage to a circuit module that alternates between normal and drowsy operating modes.

REFERENCES:
patent: 5552740 (1996-09-01), Casper
patent: 6111394 (2000-08-01), Casper
patent: 6281744 (2001-08-01), Kang
patent: 6380799 (2002-04-01), Chung et al.
patent: 6509786 (2003-01-01), Uekubo
patent: 6560139 (2003-05-01), Ma et al.
patent: 6836179 (2004-12-01), Mizuno et al.
patent: 6906582 (2005-06-01), Kase et al.
patent: 6909320 (2005-06-01), Chan et al.
patent: 6933772 (2005-08-01), Banerjee et al.
patent: 7064601 (2006-06-01), Kwak et al.
patent: 7091712 (2006-08-01), Miller et al.
patent: 7099230 (2006-08-01), Tran
patent: 7110317 (2006-09-01), Song et al.
patent: 7126861 (2006-10-01), Hose, Jr. et al.
patent: 7135842 (2006-11-01), Banerjee et al.
patent: 7235959 (2007-06-01), Sicard
patent: 7253595 (2007-08-01), Oddoart et al.
patent: 7268524 (2007-09-01), Kase et al.
patent: 7414457 (2008-08-01), Ogawa et al.
patent: 7423416 (2008-09-01), Quinones et al.
patent: 7432693 (2008-10-01), Enjalbert
patent: 7439718 (2008-10-01), Rozen et al.
patent: 7441137 (2008-10-01), Mimberg
patent: 7463013 (2008-12-01), Plojhar
patent: 7479824 (2009-01-01), Bushman et al.
patent: 7554312 (2009-06-01), Fulton et al.
patent: 7619440 (2009-11-01), Amedeo et al.
patent: 2009/0096433 (2009-04-01), Gerber et al.
Nii et al.: “A 90 nm Low Power 32K-Byte Embedded SRAM with Gate Leakage Suppression Circuit for Mobile Applications”; 2003 Symposium on VLSI Circuits Digest of Technical Papers; 2003; pp. 247-250; IEEE.
Tschanz et al.; “Dynamic Sleep Transistor and Body Bias for Active Leakage Power Control of Microprocessors”; IEEE Journal of Solid State Circuits; Nov. 2003; pp. 1838-1845; vol. 38, No. 11. IEEE.
Bhavnagarwala et al.; “A Pico-Joule Class, 1 GHz, 32 KByte×64b DSP SRAM with Self Reverse Bias”; 2003 Symposium of VLSI Circuits Digest of Technical Papers; 2003; pp. 251-252; IEEE.
Chang et al.; “The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series”; IEEE Journal of Solid-State Circuits; Apr. 2007; pp. 846-852; vol. 42, No. 4; IEEE.
Vangal et al.;“An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS”; IEEE Journal of Solid-State Circuits; Jan. 2008; pp. 29-41; vol. 43, No. 1; IEEE.

Affiliated with

Also associated with

Rating

Circuit for a low power mode does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit for a low power mode, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit for a low power mode will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4241510