Telephonic communications – Diagnostic testing – malfunction indication – or electrical... – Of centralized switching system
Patent
1994-02-04
1996-05-21
Chin, Stephen
Telephonic communications
Diagnostic testing, malfunction indication, or electrical...
Of centralized switching system
379 21, 379394, 379398, 379414, H04M 308, H04M 124, H04M 900, H04M 176
Patent
active
055197558
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The present invention relates to a circuit for a line simulating device for simulating the transmission characteristics of lines carrying digital signals, such as bus lines operable in ISDN networks.
The transmission parameters of a line often must be simulated to investigate the transmission characteristics of bus lines in a system mentioned at the outset, composed of a network termination, the line, and the peripherals attached thereto. A natural simulation of the transmission characteristics of buses operated in the system, over which digital signals are transmitted, for example, is possible with the line simulation afforded by the circuit of the present invention.
The known CCITT guideline for line simulation is incomplete regarding the various designs of the lines used. This is unacceptable since various lines have very different transmission characteristics, especially at frequencies above 100 kHz, and display equivalence corresponding to the CCITT guideline only at a frequency of 96 kHz.
Therefore, there exists a need for a circuit for stimulating different line designs in a simple manner.
SUMMARY OF THE INVENTION
The present invention provides a circuit which meets the above-mentioned need. In the circuit of the present invention: devices, each stimulating a specific partial line length and the maximum line length of the line to be stimulated being expressed in multiples of the partial line length; each is equipped with a transformer-coupled circuit part A, short-circuited at the input by a first capacitor unit, a transformer-coupled circuit part B with its windings being center tapped and short-circuited by a second capacitor unit, and a circuit part C on the line plane with the DC resistance on the input and output sides, each being short-circuited by a third capacitor unit, which is connected on the output side in mirror-image sequence with another circuit part B and a following additional circuit part A; (R1) and (R3) wired in parallel with a first inductance composed of winding N1; resistance (R2) and (R4) wired in parallel with the inductance composed of windings N2+N3; and capacitor unit.
With the structured circuit according to the present invention, all the values for the resistances, inductances, and capacitances for a certain line design can be determined from information provided by the manufacturer of the lines (i.e., resistance per unit length R* (Ohm/kin), inductance per unit length L* (H/km), and capacitance per unit length C* (F/km)), with the known means of evolution strategy. Details of evolution strategy are available in the book "Evolution Strategy" by Ingo Rechenberg, Fromann-Holzboog, Stuttgart-Canstatt, 1973, and "VDI Progress Reports 1982," by Martin Ruppert. While the various line designs produce correspondingly different combinations of the values for resistances R0, R1, to R4, for inductances L1, L2, and for capacitances C1 to C3, the individual components are always arranged according to the present invention. Since the line simulations form the transmission characteristics of the different designs of the lines, measurements directly on cable drams can be eliminated. On the other hand, the so-called extension line known from DE-PS 500 371 permits only integral multiplications of a given damping value by a so-called root line. The root line is connected twice in series for example, to produce twice the damping value.
In the present invention, standardized partial line simulating devices are provided, each simulating device representing a specific line length. In such an arrangement, a corresponding multiplication of the line simulation can be implemented in simple fashion for a wide variety of different line lengths. In this connection, in addition to the multiplying the partial line simulating devices, their individual values may be designed with variable resistances, inductances, and capacitances by suitable circuit measures. As a result in practice, a universal line simulation for the most diverse line designs with the greatest differen
REFERENCES:
patent: 1533178 (1925-04-01), Gilbert
patent: 3745261 (1973-07-01), Friedman
patent: 3823281 (1974-08-01), Chambers
patent: 3932712 (1976-01-01), Suntop
patent: 3956601 (1976-05-01), Harris
patent: 4852160 (1989-07-01), Kiko
patent: 4866767 (1989-09-01), Tanimoto
patent: 5173896 (1992-12-01), Dariano
Chin Stephen
Shankar Vijay
Siemens Aktiengesellschaft
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