Coded data generation or conversion – Converter compensation
Patent
1997-01-04
1998-09-22
Gaffin, Jeffrey A.
Coded data generation or conversion
Converter compensation
341120, 341155, 341156, H03M 106
Patent
active
058120777
ABSTRACT:
There is disclosed an A/D conversion circuit comprising a first A/D converter for receiving an input signal of the A/D conversion circuit and providing a digital output signal, the first A/D converter having a restricted resolution, wherein the input signal passes through delay means to a first input of a subtraction stage. A first D/A converter operating on the output signal of the first A/D converter generates an analog output signal and feeds the analog output signal via an adding stage to a second and subtracting input of the subtraction stage, wherein the input signal of the first D/A converter passes through a correction algorithm unit to a second D/A converter. The output signal of the second D/A converter is fed to a second input of the adding stage, wherein the correction algorithm unit provides empirically determined data for D/A conversion correction. A low pass filter coupled to the output of the subtraction stage provides a low pass filtered and amplified output signal. A sample-and-hold circuit then passes the low pass filtered and amplified output signal of the subtraction stage to the input of a second A/D converter, wherein the first A/D converter and the first D/A converter are controlled by a clock having a frequency which is substantially greater than the frequency of another clock which controls the sample-and-hold circuit and the second A/D converter. A summing stage sums the output signals of the first and second A/D converters to form an output signal of the A/D conversion circuit.
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Gaffin Jeffrey A.
Kost Jason L. W.
Thomson Multimedia S.A.
Tripoli Joseph S.
Wein Frederick A.
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