Circuit fabrication

Metal working – Method of mechanical manufacture – Electrical device making

Reexamination Certificate

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Details

C029S852000, C216S013000, C216S017000, C216S018000

Reexamination Certificate

active

06360434

ABSTRACT:

BACKGROUND OF THE INVENTION
Electronic circuits included on circuit boards often have thickened metallized areas serving as terminal pads which allow electrical devices to be wire bonded thereto. Conventional methods for forming such circuits usually involve forming a photoresist pattern on a copper clad circuit board substrate and electro-plating a thick patterned layer of copper over the copper cladding. Areas of copper are etched away to produce a desired circuit pattern on the circuit board substrate. The thickened areas of the circuit are suitable for wire bonding to electronic devices.
A drawback with such a method is that etching the unneeded areas of copper from the circuit board substrate usually requires a relatively long etching process due to the thickened layers of metal. As a result, the side edges of the circuit pattern often become undercut and/or ragged which can affect the performance of the circuit. In addition, temporary bussing pathways may be formed to provide electrical continuity between different portions of the circuit board substrate or between opposite sides thereof. The electrical continuity is required for providing electrical current to areas where the deposition of metallic material by electro-plating or electrolytic deposition is desired. The temporary bussing pathways are later etched away in another etching process. The added etching process may affect the quality of the side edges of the remaining portions of the circuit pattern.
SUMMARY OF THE INVENTION
The present invention provides a method of forming a circuit on a circuit board including thickened areas suitable for wire bonding to electrical devices where the traces of the circuit have limited undercutting and can be manufactured with higher tolerances than possible with previous methods. The method includes forming a metallic circuit pattern on a base substrate. The circuit pattern has traces which are connected together by temporary bussing. A resist pattern is formed over the circuit pattern for defining at least one terminal pad. A layer of metal is formed on at least one area of the circuit pattern exposed by the resist pattern to a thickness suitable for serving as the at least one terminal pad for the circuit. A portion of the base substrate at the location of the temporary bussing is removed, thereby causing the removal of the temporary bussing.
In preferred embodiments, the metallic circuit pattern is formed by forming a first resist pattern for defining the circuit pattern over a metallic layer on the base substrate. Areas of the metallic layer on the base substrate exposed by the first resist pattern are etched away thereby forming the metallic circuit pattern under the first resist pattern. The first resist pattern is then stripped from the base substrate to uncover the circuit pattern. The circuit pattern and its side edges are covered with a protective metallic layer. The protective metallic layer is formed by forming a metallic inner barrier layer over the circuit pattern and side edges thereof by electroless deposition and then forming a metallic outer layer over the barrier layer also by electroless deposition.
The base substrate preferably has opposing sides each with a metallic layer thereon. In such a case, before forming the metallic circuit pattern, at least one via hole is formed through the base substrate. A conductive pathway is formed through the at least one via hole to provide electrical continuity between the metallic layers on the opposing sides of the base substrate. The conductive pathway later becomes part of the temporary bussing when the circuit pattern is formed. The conductive pathway may be formed by first forming a thin metallic layer within the at least one via hole and over the metallic layers of the base substrate by electroless deposition, and then forming a thick metallic layer over the thin layer as well as within the at least one via hole by electrolytic deposition. The metallic layer which forms the at least one terminal pad is deposited by electrolytic deposition.
In one embodiment, the metallic layers of the base substrate which are on opposing sides of the base substrate are made of copper. The conductive pathway is formed by first forming a thin copper layer within the at least one via hole and over the copper layers of the base substrate by electroless copper deposition, and then forming a thick copper layer over the thin layer by electrolytic copper deposition. Consequently, after etching, the resulting metallic circuit pattern is made of copper. The protective metallic layer is formed by forming an inner barrier layer of nickel over the circuit pattern and side edges thereof by electroless nickel deposition and then forming an outer layer of gold over the inner barrier layer of nickel by electroless gold deposition. The terminal pads are formed by electrolytic gold deposition. Finally, the temporary bussing is routed out with a router.
In another embodiment, the metallic circuit pattern is formed by providing the base substrate with a metallic layer thereon. A first resist pattern is formed over the metallic layer on the base substrate for defining the circuit pattern. Next, the thickness of the metallic layer is increased in areas of the base substrate exposed by the first resist pattern. The thickened metallic layer in the areas exposed by the first resist pattern is later covered with a protective metallic layer. The first resist pattern is then stripped from the base substrate. Finally, areas of the base substrate not protected by the protective metallic layer are etched from the base substrate, thereby forming the metallic circuit pattern.
In the present invention, since the circuit pattern is etched before the thick layer of metal forming the terminal pads is deposited, the etching is performed on a relatively thin layer of metal for a relatively short period of time. As a result, the side edges of the traces of the circuit pattern once formed, are not subjected to a lengthy attack by the etchant and experience very little etching and/or undercutting. In addition, by removing the temporary bussing by routing, the circuit pattern is not subjected to any further etching steps, thereby preserving the quality of the side edges of the traces. Consequently, the present invention is suitable for forming very fine and delicate traces with high yield as well as with high performance.


REFERENCES:
patent: 3990926 (1976-11-01), Konicek
patent: 4053370 (1977-10-01), Yamashita et al.
patent: 4104111 (1978-08-01), Mack
patent: 4325780 (1982-04-01), Schulz, Sr.
patent: 4444619 (1984-04-01), O'Hara
patent: 4605471 (1986-08-01), Mitchell
patent: 4925525 (1990-05-01), Oku et al.
patent: 5733468 (1998-03-01), Conway, Jr.

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