Circuit die having improved substrate noise isolation

Details Circuit die having improved substrate noise isolation Circuit die having improved substrate noise isolation

1994-06-30

1995-12-12

Limanek, Robert P.

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

With pn junction isolation

257659, 257394, 257901, H01L 2706, H01L 2941

Patent

active

054752558

ABSTRACT:
A circuit die 100 with improved substrate noise isolation may be achieved by providing a first circuit element 102 and a second circuit element 103 on a substrate 101. The first circuit element 102 generally injects noise into the substrate 101 while the second circuit element 103 is adversely affected by noise being carried in the substrate 101. To reduce the noise interference, a noise isolation ring 104-017 may be placed around the first circuit element 102 and/or the second circuit element 103 wherein the noise isolation ring is of a conducted material. A first lead 202 is electrically connected to a first circuit element 102, a second lead 205 is electrically connected to the second circuit element 103, and a third lead 201 is electrically connected to the noise isolation ring 105, wherein the third lead 201 is electrically isolated from both the first and second leads 202 and 205.

REFERENCES:
patent: 4470062 (1984-09-01), Muramatsu
patent: 5196920 (1993-03-01), Kumamoto et al.

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