Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-07-12
2002-12-10
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S230060
Reexamination Certificate
active
06493268
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit device adapted to perform hierarchic row decoding in semiconductor memory devices.
The invention relates, particularly but not exclusively, to a device as above, which is adapted to perform hierarchic row decoding in non-volatile semiconductor memory devices comprising at least one array of memory cells with column-ordered sectors, wherein each sector has a respective local wordline group linked to a main wordline, the circuit device having a main wordline driver provided at each main wordline and a local decoder provided at each local wordline.
One of the most widely used memory array architectures in the manufacture of non-volatile memory devices integrated in a semiconductor, is a NOR type. In such architecture, memory cells that locate in the same row of the array have their gate terminals in common, and memory cells that locate in the same array column have their drain terminals in common. Moreover, all the cells in an array sector have their source terminals in common.
To individuate a particular memory location, it is sufficient that a given row and a given column be selected, for only one memory cell can situate at their intersection. In non-volatile memories, a cell comprises a floating gate transistor having, moreover, drain and source conduction terminals.
The solution proposed has a specific application to decode architectures of the hierarchic type and reference will be made to such architectures for convenience of illustration.
2. Description of the Related Art
A first known type of architecture for non-volatile memory arrays comprises row-ordered sectors and corresponding row decoders associated with each sector.
This architecture uses up much circuit space, since a decoder for each sector must be provided, as well as local column decoders, to avoid the “drain stress” phenomenon.
It is important to further consider that the memory array rows are materialized by polysilicon stripes laid to interconnect all the gate terminals of cells in one row.
From an electrical standpoint, each polysilicon stripe may be regarded as a distributed RC network. For example, the time constant of an array row defined by the RC network is approximately 10 ns, even when the number of cells is relatively small, e.g., 1024.
The above time value represents the time required for an electric signal to propagate through an array row, and directly affects the memory access time, which is required to be the shortest possible, as is well known.
Owing to the high density of cell integration in the integrated memory circuit, the local bitlines and the main bitline are formed by a process that consists of depositing two different layers or metal levels; short-circuiting the polysilicon row and shortening the row charge time become impossible unless a third metal level is provided.
Another known technical solution provides for the non-volatile memory arrays to be column-ordered. In this case, the array rows are shared by all sectors, and the size of a sector is set by the number of columns.
With an architecture of that type, the parasitic capacitance of each bitline is kept quite low, this being of substantial benefit to the circuit portion that is to read the memory contents.
Also, row decoding can be shared by several sectors, with attendant savings of circuit space.
Where an array is fabricated using a technological process that provides for two metal levels, one level is utilized to form the bitlines and the other level utilized to short-circuit the row for lower parasitic resistance during the charging phase.
Although advantageous on many counts, this prior architecture also has a drawback in that, each time that a cell is addressed, all the cells in the same row are biased and subjected to “gate stress”.
Furthermore, the information stored in non-volatile memories of the flash EEPROM type must be erased in groups or packets of bits. Erasing is the single operation where the source terminal is biased, and since all the cells have this terminal in common, they must be erased simultaneously, even though they can be written and read independently.
More particularly, flash memories are erased by the sector, meaning that all the cells linked to the same source line are erased simultaneously.
A circuit device adapted to perform erasings by negative voltages in column-ordered memory arrays is disclosed in the Applicant's Published European Patent Application No. 0 991 075. This device is also shown schematically in
FIG. 1
in relation to a single array sector, generally designated
1
.
It should be noted that the cells contained in the sectors of the non-volatile memory array associated with the device
1
are ordered into plural wordlines or local rows, designated LWL (Local Word Line). In parallel with each array row, a main row- or wordline is provided, which is designated MWL (Main Word Line) and extends through all the sectors that have main rows in common. Within each sector, the circuit device
1
is connected upstream of each local wordline LWL of the memory array.
The memory device is supplied a single supply voltage Vdd, in the range of 2.5 to 3.6 Volts, and is connected to a second reference voltage GND, e.g., a signal ground.
The device
1
comprises a plurality of local decoders
2
connected between each local wordline LWL and the main wordline MWL, to which said local lines are linked.
The device
1
further includes, provided at each main wordline MWL, a main wordline driver
3
, which comprises basically a pair of MOS transistors mounted in a pull-up/pull-down configuration and connected between first TVGLOB and second TSRC bias terminals to correspondingly receive first VGLOB and second SRC bias signals.
Each local decoder
2
comprises a first transistor M
1
of the PMOS type having one of its conduction terminals connected to the main wordline MWL and the other connected to the local wordline LWL.
The body terminal of transistor M
1
receives the first bias signal VGLOB, its gate terminal receiving a first tripping signal PCH.
The gate terminals of all the transistors M
1
of the local decoders
2
associated with the array rows in one sector are connected together and receive the same voltage signal.
The local decoder
2
further comprises a second transistor M
2
of the NMOS type having one of its conduction terminals connected to the main wordline MWL and the other connected to the local wordline LWL.
The body terminal of transistor M
2
receives the second bias signal SRC at a negative voltage (about −8V) during the erase phase, and the transistor gate terminal receives a second tripping signal NCH. The value of the second bias signal SRC is 0V (GND) for the other operations.
The gate terminals of all the transistors M
2
of the local decoders
2
associated with the array rows in one sector are connected together and receive the same voltage signal.
Advantageously, an NMOS transistor M
3
is connected with its conduction terminals between the local wordline LWL and the second bias terminal TSRC, the latter receiving the second bias voltage SRC as a negative voltage during the erase phase, and the signal ground GND for the other operations.
The body terminal of transistor M
3
is connected to the second bias terminal TSRC, its gate terminal receiving a signal DISCH.
The gate terminals of all the transistors M
3
of the local decoders
2
associated with the array rows in one sector are connected together and receive the same voltage signal.
In essence, this circuit device performs a row decoding of the hierarchic type by virtue of an additional transistor M
3
in the local decoders
2
having one conduction terminal connected to the local wordline and the other connected to a ground voltage reference.
The technological trend toward the use of devices with ever higher cuts and densities in the field of memory devices poses important design problems, which are well recognized and have power consumption in the various modes (read, program, erase, etc.) of the device oper
Gregori Stefano
Khouri Osama
Micheloni Rino
Pierin Andrea
Sangalli Miriam
Iannucci Robert
Jorgenson Lisa K.
Nguyen Tan T.
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
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