Electrical pulse counters – pulse dividers – or shift registers: c – Shift register – Particular transfer means
Patent
1994-03-08
1996-05-14
Heyman, John S.
Electrical pulse counters, pulse dividers, or shift registers: c
Shift register
Particular transfer means
377 74, 345197, G11C 1928
Patent
active
055175430
ABSTRACT:
The circuit device has a plurality of cascaded stages. Each cascaded stage includes several partial stages and has at most two capacitors (C.sub.n1, C.sub.nB) and at most seven transistors (T.sub.n1, T.sub.n2, T.sub.n3, T.sub.n4, T.sub.n5, T.sub.n6, T.sub.n7). The circuit device includes a device for controlling the cascaded stages with four periodic clock signals (.PHI..sub.1, .PHI..sub.2, .PHI..sub.3, .sub.101 .sub.4) phase-shifted about 90.degree. relative to each other such that each of the cascaded stages is controlled by a respective assigned one of four predetermined sets of two of the four periodic clock signals and the same one of the four predetermined set repeats every fifth cascaded stage. Each cascaded stage includes an output stage (12, 12') including a bootstrap-capacitor (C.sub.nB) and three transistors (T.sub.n5, T.sub.n6, T.sub.n7) electrically connected to the bootstrap-capacitor (C.sub.nB); and a charging and discharging stage (11) for the bootstrap-capacitor (C.sub.nB). The charging and discharging stage (11) includes at least one transistor (T.sub.n4) connected electrically to the bootstrap capacitor (C.sub.nB). Each cascaded stage can advantageously also include an inverter stage connected to the charging and discharging stage and including two transistors (T.sub.n1, T.sub.n2) and a memory capacitor (C.sub.n1) electrically connected with each other and controlled by an input signal so that so that both transistors (T.sub.n1, T.sub.n2) are never simultaneously conducting.
REFERENCES:
patent: 3483400 (1969-12-01), Washizuka et al.
patent: 3576447 (1971-04-01), McKenny
patent: 3676709 (1972-07-01), Ducamus et al.
patent: 4084106 (1978-04-01), Ullrich
patent: 4623908 (1986-11-01), Oshima et al.
patent: 5136622 (1992-08-01), Plus
patent: 5222082 (1993-06-01), Plus
Fischer, A., "Flache Fernseh-Bildschirme", ntz vol. 33, 1980, pp. 80-88.
Y. Oana, et al, 1984 SID Symposium Digest, pp. 312-315.
S. Morozumi, et al, 1984 SID Symposium Digest, pp. 316-319.
J. Onwada, et al, Conf. record of the 1988 Inter. Res. Conf., pp. 215-219.
B. W. Faughnan, et al, Proceedings of the SID, vol. 29/4, 1988, pp. 279-282.
I. De Rycke, et al, Conf. record of the 1988 Inter. Res. Conf., pp. 70-73.
M. Akiyama, et al, Japan Display 1986, pp. 212-215.
K. Khakzar, et al, Japan Display 1989, pp. 438-441.
Y. Nishihara, et al, 1992 SID Symposium Digest, pp. 609-612.
Dae M. Kim, et al, 1990 SID Sympoisum Diges, pp. 304-306.
Luder Ernst
Schleupen Kai
Heyman John S.
Lueder Ernst
Striker Michael J.
LandOfFree
Circuit device for controlling circuit components connected in s does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit device for controlling circuit components connected in s, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit device for controlling circuit components connected in s will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1902915