Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2000-09-27
2003-04-15
Thomas, Tom (Department: 2811)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S110000, C438S112000, C438S123000, C438S124000, C438S125000, C438S126000, C438S127000, C438S128000, C257S737000, C257S738000, C257S780000, C257S778000, C257S787000, C257S784000, C257S666000
Reexamination Certificate
active
06548328
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit device and a method for manufacturing the circuit device, and more particularly to a thin-type circuit device and a method of manufacturing the thin-type circuit device without the need of providing a support substrate.
2. Description of the Related Art
Conventionally, it has been demanded that a circuit device which is set in an electronic apparatus is reduced in size, thickness and weight, because the circuit device is used for a portable telephone, a portable computer and so on.
For example, a semiconductor device as a circuit device is typically a package type semiconductor device which is conventionally sealed by normal transfer molding. This semiconductor device
1
is mounted on a printed circuit board PS as shown in FIG.
24
.
This package type semiconductor device
1
has a semiconductor chip
2
covered with a resin layer
3
, with a lead terminal
4
for external connection derived from the side of this resin layer
3
.
However, this package type semiconductor device
1
had the lead terminal
4
out of the resin layer
3
, and was too large in total size to meet smaller, thinner and lighter requirements.
Therefore, various companies have competed to develop a wide variety of structures which are reduced in size, thickness and weight. Recently, a wafer scale CSP which is as large as a chip size, called a CSP (Chip Size Package), or a CSP which is slightly larger than the chip size, has been developed.
FIG. 25
shows a CSP
6
which adopts a glass epoxy substrate
5
as a support substrate and which is slightly larger than a chip size. Herein, a transistor chip T is mounted on the glass epoxy substrate
5
.
On the surface of this glass epoxy substrate
5
, a first electrode
7
, a second electrode
8
and a die pad
9
are formed, and on the back face, a first back electrode
10
and a second back electrode
11
are formed. Via a through hole TH, the first electrode
7
and the first back electrode
10
, as well as the second electrode
8
and the second back electrode
11
, are electrically connected. On the die pad
9
, the bare transistor chip T is fixed. An emitter electrode of transistor and the first electrode
7
are connected via a bonding wire
12
, and a base electrode of transistor and the second electrode
8
are connected via the bonding wire
12
. Further, a resin layer
13
is provided on the glass epoxy substrate
5
to cover the transistor chip T.
The CSP
6
adopts the glass epoxy substrate
5
, which has the merits of a simpler structure extending from the chip T to the back electrodes
10
,
11
for external connection, and a less expensive cost of manufacture, than the wafer scale CSP.
The CSP
6
is mounted on the printed circuit board PS, as shown in FIG.
24
. The printed circuit board PS is provided with the electrodes and wires making up an electric circuit, and has the CSP
6
, the package type semiconductor device
1
, a chip resistor CR and a chip capacitor CC fixed for the electrical connection.
A circuit on this printed circuit board is packaged in various sets.
Referring to
FIGS. 26 and 27
, a method for manufacturing this CSP will be described below. In
FIG. 27
, reference is made to a flow diagram entitled as a Glass epoxy/flexible substrate, listed in the middle.
Firstly, the glass epoxy substrate
5
is prepared as a base material (support substrate). On both sides of the glass epoxy substrate
5
, the Cu foils
20
,
21
are applied via an insulating adhesive (see FIG.
26
A).
Subsequently, the Cu foils
20
,
21
corresponding to the first electrode
7
, the second electrode
8
, the die pad
9
, the first back electrode
10
and the second back electrode
11
are coated with an etching resist
22
and patterned. Note that the patterning may be made separately on the front face and the back face (see FIG.
26
B).
Then, using a drill or a laser, a bore for the through hole TH is opened in the glass epoxy substrate. This bore is plated to form the through hole TH. Via this through hole TH, the electrical connection between the first electrode
7
and the first back electrode
10
and between the second electrode
8
and the second back electrode
10
is made (see FIG.
26
C).
Further, though being not shown in the figure, the first electrode
7
and the second electrode
8
which become the bonding posts are subjected to Ni plating or Au plating, and the die pad
9
which becomes a die bonding post is subjected to Au plating to effect die bonding of the transistor chip T.
Lastly, the emitter electrode of the transistor chip T and the first electrode
7
, and the base electrode of the transistor chip T and the second electrode
8
are connected via the bonding wire
12
, and covered with the resin layer
13
(see FIG.
26
D).
As required, individual electrical elements are formed by dicing. In
FIG. 26
, only one transistor chip T is provided on the glass epoxy substrate
5
, but in practice, a matrix of transistor chips T are provided. Accordingly, a dicing apparatus separates them into individual elements.
In accordance with the above manufacturing method, a CSP type electrical element using the support substrate
5
can be completed. This manufacturing method is also effected with the use of a flexible sheet as the support substrate.
On the other hand, a manufacturing method adopting a ceramic substrate is shown in a flow diagram to the left in FIG.
27
. After the ceramic substrate which is the support substrate is prepared, the through holes are formed. Then using a conductive paste, the electrodes are printed and sintered on the front face and the back face. Thereafter, the same manufacturing method of
FIG. 26
, up to coating the resin layer is followed, but since the ceramic substrate is very fragile, and is likely to break off, unlike a flexible sheet or the glass epoxy substrate, there is a problem with the difficulty of molding using die. Therefore, a sealing resin is potted and cured, then polished for the uniform treatment of the face of the sealing resin. Lastly, using the dicing apparatus, individual devices are made.
In
FIG. 25
, the transistor chip T, connecting means
7
to
12
, and the resin layer
13
are requisite components for the electrical connection with the outside, and the protection of transistor. However, only these components were difficult to provide an electrical circuit device reduced in size, thickness and weight.
Essentially, there is no need of having the glass epoxy substrate
5
which becomes the support substrate, as described before. However, since the manufacturing method involves pasting the electrode on the substrate, the support substrate is required, and this glass epoxy substrate
5
could not be dispensed with.
Accordingly, the use of this glass epoxy substrate
5
raised the cost. Further, since the glass epoxy substrate
5
was thick, the circuit device was thick, limiting the possibility to reduce the size, thickness and weight of the device.
Further, the glass epoxy substrate or the ceramic substrate necessarily requires a through hole forming process for connecting the electrodes on both sides. Hence, there was a problem with the long manufacturing process.
FIG. 28
shows a pattern diagram on the glass epoxy substrate, the ceramic substrate or a metal substrate. On this pattern, an IC circuit is typically made, with a transistor chip
21
, an IC chip
22
, a chip capacitor
23
and/or a chip resistor
24
mounted. Around this transistor chip
21
or the IC chip
22
, a bonding pad
26
integral with a wire
25
is formed to electrically connect the chips
21
,
22
via a bonding wire
28
. A wire
29
is made integrally with an external lead pad
30
. These wires
25
,
29
are bent through the substrate, and made slender in the IC circuit, as necessary. Accordingly, this slender wire has smaller contact area with the substrate, leading to exfoliation or curvature of the wire. The bonding pad
26
is classified into a bonding pad for power and a bonding pad for small signal. Parti
Kobayashi Yoshiyuki
Maehara Eiju
Mashimo Shigeaki
Okawa Katsumi
Sakamoto Junji
Fish & Richardson PC
Parekh Nitin
Sanyo Electric Co,. Ltd.
Thomas Tom
LandOfFree
Circuit device and manufacturing method of circuit device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit device and manufacturing method of circuit device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit device and manufacturing method of circuit device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3013757