Circuit design technique to prevent current hogging when minimiz

Details Circuit design technique to prevent current hogging when minimiz Circuit design technique to prevent current hogging when minimiz

1981-09-14

1987-07-21

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307446, 307458, 307477, H03K 19091

Patent

active

046820574

ABSTRACT:
An STL or ISL logic circuit comprising a plurality of single-input, multiple-output logic gates is provided. Each of these gates has a current source and a transistor including a base, emitter and multiple Schottky diode-to-collector contacts. The bases of the logic gate transistors are tied together to minimize metal interconnect stripes when a fanout greater than that of one gate is needed. Current hogging is reduced by an ohmic collector contact with connects the collector of each transistor together.

REFERENCES:
patent: 3918004 (1975-11-01), Shimizu et al.
patent: 4129790 (1978-12-01), Gani et al.
patent: 4165470 (1979-08-01), Fulkerson
patent: 4288805 (1981-09-01), Depey
Taub and Schilling, Digital Integrated Electronics, McGraw-Hill, Inc., New York, 1977, pp. 164-169.

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