Circuit connection information generation through circuit analys

Details Circuit connection information generation through circuit analys Circuit connection information generation through circuit analys

1995-02-22

1997-05-20

Teska, Kevin J.

Boots, shoes, and leggings

H05K 702

Patent

active

056318413

ABSTRACT:
A circuit connection information generating device for generating circuit connection information which correctly reflects circuit connection information provided from a circuit drawing and which contains parasitic elements is disclosed. A node/element name converting means (4) replaces the name of a component to be converted which is specified by first circuit connection information (D11) with the name of an element and node specified by second circuit connection information on the basis of a corresponding relation of the component to be converted when the corresponding relation is indicated in a node/element name correspondence table (D1) and replaces the name of the component to be converted with a name sequentially given from an unused name list (NL) when the corresponding relation is not indicated in the node/element name correspondence table (D1), to provide third circuit connection information (D13) on the basis of the node/element name correspondence table (D1), the first circuit connection information (D11), and the unused name list (NL).

REFERENCES:
patent: 5249133 (1993-09-01), Batra
patent: 5278769 (1994-01-01), Bair et al.
patent: 5463563 (1995-10-01), Bair et al.
patent: 5469366 (1995-11-01), Yang et al.
IEEE Transactions on Computer-Aided Design, vol. 11, No. 6, pp. 732-738, Jun. 1992, Terrence B. Hook, "Automatic Extraction of Circuit Models from Layout Artwork for a BiCMOS Technology".
An Interactive Layout Design System with Real-Time Logical Verification and Extraction of Layout Parasitics, IEEE 1988.
Detailed Extraction of Distributed Networks and Parasitics in IC Designs IEEE, 1992.

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